Voltage supply for operating a plurality of changing transistors in a manner which reduces minority carrier disruption of adjacent memory cells

Claim 2

A MOS integrated circuit device comprising: a plurality of charge retention circuit elements formed on a semiconductor substrate; a peripheral circuit for operation of said charge retention circuit elements having charging transistors which provide logic signals at their source electrodes, said charging transistors being formed on the semiconductor substrate and positioned near to the charge retention circuit elements, a first voltage being applied to the gate electrodes of said charging transistors; and voltage supply means formed on the semiconductor substrate for supplying a second voltage to the drain electrodes of said charging transistors, said second voltage cooperating with said first voltage to operate the charging transistors in a triode region for a predetermined time thereby to prevent the charge retention characteristics of the charge retention circuit elements from being degraded.

Claim 3

A MOS integrated circuit device comprising: a plurality of charge retention circuit elements formed on a semiconductor substrate; a peripheral circuit for operation of said charge retention circuit elements having charging transistors which provide logic signals at their source electrodes, said charging transistors being formed on the semiconductor substrate and positioned near to the charge retention circuit elements, a logic one level voltage being applied to the gate electrodes of said charging transistors for a predetermined time; and voltage supply means formed on the semiconductor substrate for supplying to the drain electrodes of said charging transistors a voltage which is lower than the logic one level voltage by about the threshold voltage of the charging transistors to operate said charging transistors in a manner which prevents the charge retention characteristics of the charge retention circuit elements from being degraded, and with a plurality of said charging transistors coupled to one voltage supply means to minimize the number of minority carriers introduced into said substrate.

Claim 4

A MOS integrated circuit device comprising: a plurality of charge retention circuit elements formed on a semiconductor substrate; a peripheral circuit for operation of said charge retention circuit elements having charging transistors which provide logic signals at their source electrodes, said charging transistors being formed on the semiconductor substrate and positioned near to the charge retention circuit elements, a logic one level voltage being applied to the gate electrodes of said charging transistors for a predetermined time; and voltage supply means formed on the semiconductor substrate for supplying to the drain electrodes of said charging transistors a voltage which is lower than the logic one level voltage by about the threshold voltage of the charging transistors to operate said charging transistors in a manner which prevents the charge retention characteristics of the charge retention circuit elements from being degraded, and with a plurality of said charging transistors coupled to one voltage supply means to minimize the number of minority carriers introduced into said substrate.

Claim 5

A MOS integrated circuit device according to claim 2, wherein said voltage supply means includes a voltage supply terminal coupled to at least one MOS transistor.

Claim 6

A MOS integrated circuit device according to claim 3, wherein said MOS transistor has its gate electrode connected to its drain electrode and its source electrode connected to the drain electrodes of the charging transistors.

Claim 7

A MOS integrated circuit device according to claim 3, wherein the gate electrode of said MOS transistor is connected to a logic one level voltage source through a resistance element, and the drain-source current path of said MOS transistor is connected between said voltage supply terminal and said drain electrodes of said charging transistors.

Claim 8

A MOS integrated circuit device according to claim 3, wherein the gate electrode of said MOS transistor is supplied with a clock signal whose logic one level is a high power source voltage, and the drain-source current path of said MOS transistor is connected between said voltage supply terminal and said drain electrodes of said charging transistors.

Claim 9

A MOS integrated circuit device according to claim 3, wherein said logic one level voltage supplied to gate electrodes of the charging transistors is lower than a high power source voltage by the threshold voltage of the charging transistors, and wherein said voltage supply means comprises a first MOS transistor and a second MOS transistor, said first MOS transistor having its drain electrode connected to a high power source, its source electrode connected to the drain electrode of said second MOS transistor and its gate electrode connected to its own drain electrode, and said second MOS transistor having its source electrode connected to the drain electrodes of the charging transistors and its gate electrode connected to its own drain electrode.

Claim 10

A MOS integrated circuit device according to claim 3, wherein said MOS transistor has an electric transconductance which is greater than that of the charging transistors.

Claim 11

A MOS integrated circuit device comprising: a plurality of charge retention circuit elements formed on a semiconductor substrate; a peripheral circuit for operation of said charge retention circuit elements having charging transistors which provide logic signals at their source electrodes, said charging transistors being formed on the semiconductor substrate and positioned near to the charge retention circuit elements, a first pulsative voltage being applied to the gate electrodes of said charging transistors; and voltage supply means formed on the semiconductor substrate for supplying a second pulsative voltage to the drain electrodes of said charging transistors, said first pulsative voltage being higher during its rising period than the second pulsative voltage by the threshold voltage of the charging transistors to operate said charging transistors in a manner which prevents the charge retention characteristics of the charge retention circuit elements from being degraded, and with a plurality of said charging transistors coupled to one voltage supply means to minimize the number of minority carriers introduced into said substrate.

Claim 12

A MOS integrated circuit device comprising: a plurality of charge retention circuit elements formed on a semiconductor substrate; a peripheral circuit for operation of said charge retention circuit elements having charging transistors which provide logic signals at their source electrodes, said charging transistors being formed on the semiconductor substrate and positioned near to the charge retention circuit elements, a first pulsative voltage being applied to the gate electrodes of said charging transistors; and voltage supply means formed on the semiconductor substrate for supplying a second pulsative voltage to the drain electrodes of said charging transistors, said first pulsative voltage being higher during its rising period than the second pulsative voltage by the threshold voltage of the charging transistors to operate said charging transistors in a manner which prevents the charge retention characteristics of the charge retention circuit elements from being degraded, and with a plurality of said charging transistors coupled to one voltage supply means to minimize the number of minority carriers introduced into said substrate.

Claim 13

A MOS integrated circuit device according to claim 9, wherein said voltage supply means comprises a voltage supply terminal for receiving said second pulsative voltage and a MOS transistor which receives the first pulsative voltage at the gate electrode and which operates in a pentode region, and the drain-source current path of said MOS transistor is connected between said voltage supply terminal and said drain electrodes of said charging transistors.

Claim 14

A MOS integrated circuit device according to claim 10, wherein the drain electrode of said MOS transistor is connected to receive a high power source voltage.

Claim 15

A MOS integrated circuit device according to claim 9, wherein said voltage supply means is a pulse generating circuit for generating a pulse which is delayed with respect to the first pulsative voltage.

Claim 16

A MOS integrated circuit device according to claim 12, wherein said pulse generating circuit comprises a first inverter and a second inverter which are cascade-connected and is supplied with the first pulsative voltage and apply an output pulse to the drain electrodes of the charging transistors.

Claim 17

A MOS integrated circuit device according to claim 12, wherein said pulse generating circuit is a dynamic pulse generator comprising a plurality of transistors having source electrodes, gate electrodes and drain electrodes, the drain electrode of a first transistor being connected to receive a high power source voltage, the source electrode of the first transistor being connected to the drain electrode of a second transistor and held at the same potential as the drain electrode of the second transistor, the source electrode of the second transistor being connected to a low power source voltage, the gate electrode of the first transistor being coupled to the source electrode of the first transistor through a capacitor, the drain electrode of a third transistor being connected to receive the high power source voltage, the source electrode of the third transistor being connected to the drain electrode of a fourth transistor, held at the same potential as the drain electrode of the fourth transistor and connected also to the gate electrode of the first transistor, the source electrode of the fourth transistor being connected to the low power source voltage, the gate electrode of the third transistor being connected to receive a first clock pulse, the gate electrode of the fourth transistor being connected to receive a second clock pulse which is inverted with respect to the first clock pulse, the drain electrode of a fifth transistor being connected to receive the high power source voltage, the source electrode of the fifth transistor being connected to the drain electrode of a sixth transistor, held at the same potential as the drain electrode of the sixth transistor and connected also to the gate electrode of the second transistor, the source electrode of the sixth transistor being connected to the low power source voltage, the gate electrode of the fifth transistor being connected to receive said second clock pulse, the drain electrode of a seventh transistor being connected to receive the high power source voltage, the source electrode of the seventh transistor being connected to the drain electrode of an eighth transistor, held at the same potential as the drain electrode of the eighth transistor and connected also to the gate electrode of the sixth transistor and also to the low power source voltage through a capacitor, the source electrode of the eighth transistor being connected to the low power source voltage, the gate electrode of the seventh transistor being connected to receive the first clock pulse, the gate electrode of the eighth transistor being connected to receive the second clock pulse, and node where the first and second transistors are connected delivering an output pulse.

Claim 18

A MOS integrated circuit device according to any one of the preceding claims, wherein said charging transistors are connected to single-output data lines.

Claim 19

A MOS integrated circuit device according to any one of claims 1 to 14, wherein said charging transistors are connected to complementary-output data lines.

Claim 20

A MOS integrated circuit device according to any one of claims 1 to 14, wherein said charging transistors are to drive sense amplifiers.

Claim 21

A MOS integrated circuit device according to any one of claims 1 to 14, wherein said charging transistors are positioned at a distance from the charge retention circuit elements, said distance being about ten times as long as the diffusion length of minority carriers in said semiconductor substrate.

Claim 22

A MOS integrated circuit device according to any one of claims 1 to 14, wherein said charging transistors are positioned within about 500μ from the charge retention circuit elements.

Claim 23

A MOS integrated circuit device according to any one of claims 1 to 14, wherein said charging transistors are of enhancement type.

Claim 24

A MOS integrated circuit device according to any one of claims 1 to 14, wherein said charge retention circuit elements retain charge dynamically.

Claim 25

A MOS integrated circuit device according to any one of claims 1 to 14, wherein said charge retention circuit elements retain charge with assistance of a resistor having a resistance of at least 10 mΩ.

Claim 26

A MOS integrated circuit device according to any one of claims 1 to 14, wherein said charge retention circuit elements comprise floating gate memory transistors.

Claim 27

A MOS integrated circuit device according to any one of claims 1 to 14, wherein a minority carrier absorbing region is formed in the semiconductor substrate to surround at least one portion of said voltage supply means.

Claim 28

A MOS integrated circuit device according to any one of claims 1 to 14, wherein said voltage supply means is positioned at a distance from the charge retention circuit elements, said distance being about ten times longer than the diffusion length of minority carriers in said semiconductor substrate.

Claim 29

A MOS integrated circuit device according to any one of claims 1 to 14, wherein said voltage supply means is positioned at a distance from the charge retention circuit elements, said distance being longer than about 500μ.

Claim 30

A MOS integrated circuit device according to claim 26, wherein a minority carrier absorbing region is formed in the semiconductor substrate to surround at least one portion of said voltage supply means.

Claim 31

A MOS integrated circuit device according to claim 24, wherein said minority carrier absorbing region is formed so as to surround entirely the voltage supply means.

Claim 32

A MOS integrated circuit device according to claim 27, wherein said minority carrier absorbing region is formed as as to surround entirely the voltage supply means.