Differential input buffer-inverters and gates

Claim 2

An electronic circuit comprising: input means for providing a differential input formed with a noninverting input and an inverting input; a first bipolar transistor having a base directly coupled to the noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base directly coupled to the inverting input, a collector coupled to the first rail, and an emitter; a third bipolar transistor having a base, a collector directly coupled to the emitter of the first bipolar transistor, and an emitter coupled to a second voltage reference rail; a fourth bipolar transistor having a base, a collector directly coupled to the emitter of the second bipolar transistor, and an emitter coupled to the second rail; a first MOS transistor having a gate electrode directly coupled to the inverting input, a drain coupled to the emitter of the third bipolar transistor, and a source coupled to the base of the third bipolar transistor; a second MOS transistor having a gate electrode directly coupled to the noninverting input, a drain coupled to the emitter of the second bipolar transistor, and a source coupled to the base of the fourth bipolar transistor, the first and second MOS transistors being of a first type; a third MOS transistor having a gate electrode directly coupled to the inverting input, a source coupled to the first rail, and a drain coupled to the emitter of the first bipolar transistor; and a fourth MOS transistor having a gate electrode directly coupled to the noninverting input, a source coupled to the first rail, and a drain coupled to the emitter of the second bipolar transistor, the third and fourth MOS transistors being of a second MOS type opposite to the first MOS type, a pair of outputs of the circuit being available at nodes respectively at the emitters of the first and second bipolar transistors.

Claim 3

A circuit as in claim 1 wherein the noninverting and inverting inputs are substantially synchronous.

Claim 4

A circuit as in claim 2 wherein the bipolar transistors are of a first bipolar type, the first MOS type is nMOS when the first bipolar type is npn, and the first MOS type is pMOS when the first bipolar type is pnp.

Claim 5

A circuit as in claim 3 further including: a fifth MOS transistor having a gate electrode that receives the noninverting input, a drain coupled to the source of the first MOS transistor, and a source coupled to the second rail; and a sixth MOS transistor having a gate electrode that receives the inverting input, a drain coupled to the source of the second MOS transistor, and a source coupled to the second rail, the fifth and sixth MOS transistors being of the first MOS type.

Claim 6

A circuit as in claim 3 further including: a first resistor coupled between the source of the first MOS transistor and the second rail. a second resistor coupled between the source of the second MOS transistor and the second rail.

Claim 7

An electronic circuit responsive to a differential input formed with a noninverting input and an inverting input, the circuit comprising: a first bipolar transistor having a base responsive to the noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base responsive to the inverting input, a collector coupled to the first rail, and an emitter; a third bipolar transistor having a base, a collector coupled to the emitter of the first bipolar transistor, and an emitter coupled to a second voltage reference rail; a fourth bipolar transistor having a base, a collector coupled to the emitter of the second bipolar transistor, and an emitter coupled to the second rail; a first MOS transistor having a gate electrode responsive to the inverting input, a drain coupled to the emitter of the first bipolar transistor, and a source coupled to the base of the third bipolar transistor; a second MOS transistor having a gate electrode responsive to the noninverting input, a drain coupled to the emitter of the second bipolar transistor, and a source coupled to the base of the fourth bipolar transistor, the first and second MOS transistors being of a first MOS type; a third MOS transistor having a gate electrode coupled to the emitter of the second bipolar transistor, a source coupled to the first rail, and a drain coupled to the emitter of the first bipolar transistor; and a fourth MOS transistor having a gate electrode coupled to the emitter of the first bipolar transistor, a source coupled to the first rail, and a drain coupled to the emitter of the second bipolar transistor, the third and fourth MOS transistors being of a second MOS type opposite to the first MOS type, a pair of outputs of the circuit being available at nodes respectively coupled to the emitters of the first and second bipolar transistors.

Claim 8

An electronic circuit responsive to a differential input formed with a noninverting input and an inverting input, the circuit comprising: a first bipolar transistor having a base responsive to the noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base responsive to the inverting input, a collector coupled to the first rail, and an emitter; a third bipolar transistor having a base, a collector coupled to the emitter of the first bipolar transistor, and an emitter coupled to a second voltage reference rail; a fourth bipolar transistor having a base, a collector coupled to the emitter of the second bipolar transistor, and an emitter coupled to the second rail; a first MOS transistor having a gate electrode responsive to the inverting input, a drain coupled to the emitter of the first bipolar transistor, and a source coupled to the base of the third bipolar transistor; a second MOS transistor having a gate electrode responsive to the noninverting input, a drain coupled to the emitter of the second bipolar transistor, and a source coupled to the base of the fourth bipolar transistor, the first and second MOS transistors being of a first MOS type; a third MOS transistor having a gate electrode coupled to the emitter of the second bipolar transistor, a source coupled to the first rail, and a drain coupled to the emitter of the first bipolar transistor; and a fourth MOS transistor having a gate electrode coupled to the emitter of the first bipolar transistor, a source coupled to the first rail, and a drain coupled to the emitter of the second bipolar transistor, the third and fourth MOS transistors being of a second MOS type opposite to the first MOS type, a pair of outputs of the circuit being available at nodes respectively coupled to the emitters of the first and second bipolar transistors.

Claim 9

A circuit as in claim 6 wherein the noninverting and inverting inputs are substantially synchronous.

Claim 10

A circuit as in claim 7 wherein the bipolar transistors are of a first bipolar type, the first MOS type is nMOS when the first bipolar type is npn, and the first MOS type is pMOS when the first bipolar type is pnp.

Claim 11

A circuit as in claim 8 further including: a fifth MOS transistor having a gate electrode responsive to the noninverting input, a drain coupled to the source of the first MOS transistor, and a source coupled to the second rail; and a sixth MOS transistor having a gate electrode responsive to the inverting input, a drain coupled to the source of the second MOS transistor, and a source coupled to the second rail, the fifth and sixth MOS transistors being of the first MOS type.

Claim 12

A circuit as in claim 9 further including input means for providing the differential input.

Claim 13

A circuit as in claim 8 further including: a first resistor coupled between the source of the first MOS transistor and the second rail; and a second resistor coupled between the source of the second MOS transistor and the second rail.

Claim 14

An electronic circuit responsive to (a) a first differential input formed with a first noninverting input and a first inverting input and (b) a second differential input formed with a second noninverting input and a second inverting input, the circuit comprising: a first bipolar transistor having a base responsive to the first noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base responsive to the second noninverting input, a collector coupled to the first rail, and an emitter coupled to the emitter of the first bipolar transistor; a third bipolar transistor having a base, a collector coupled to the emitter of the first bipolar transistor, and an emitter coupled to a second voltage reference rail; a first MOS transistor having a gate electrode responsive to the first inverting input, a drain, and a source; and a second MOS transistor having a gate electrode responsive to the second inverting input, a drain, and a source, the first and second MOS transistors being arranged in series such that the drain and source of one are respectively coupled to the emitter of the first bipolar transistor and to the drain of the other whose source is coupled to the base of the first bipolar transistor, an output of the circuit being available at a node coupled to the emitter of the first bipolar transistor.

Claim 15

An electronic circuit responsive to (a) a first differential input formed with a first noninverting input and a first inverting input and (b) a second differential input formed with a second noninverting input and a second inverting input, the circuit comprising: a first bipolar transistor having a base responsive to the first noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base responsive to the second noninverting input, a collector coupled to the first rail, and an emitter coupled to the emitter of the first bipolar transistor; a third bipolar transistor having a base, a collector coupled to the emitter of the first bipolar transistor, and an emitter coupled to a second voltage reference rail; a first MOS transistor having a gate electrode responsive to the first inverting input, a drain, and a source; and a second MOS transistor having a gate electrode responsive to the second inverting input, a drain, and a source, the first and second MOS transistors being arranged in series such that the drain and source of one are respectively coupled to the emitter of the first bipolar transistor and to the drain of the other whose source is coupled to the base of the first bipolar transistor, an output of the circuit being available at a node coupled to the emitter of the first bipolar transistor.

Claim 16

A circuit as in claim 12 wherein (a) the first noninverting and inverting inputs are substantially synchronous and (b) the second noninverting and inverting inputs are substantially synchronous.

Claim 17

A circuit as in claim 13 wherein the MOS transistors are all of a first MOS type, the bipolar transistors are of a first bipolar type, the first MOS type is nMOS when the first bipolar type is npn, and the first MOS type is pMOS when the first bipolar type is pnp.

Claim 18

A circuit as in claim 14 further including: a third MOS transistor having a gate electrode responsive to the first noninverting input, a drain coupled to the base of the third bipolar transistor, and a source coupled to the second rail; and a fourth MOS transistor having a gate electrode responsive to the second noninverting input, a drain coupled to the base of the third bipolar transistor, and a source coupled to the second rail, the third and fourth MOS transistors being of the first MOS type.

Claim 19

A circuit as in claim 15 further including input means for providing the first and second differential inputs.

Claim 20

A circuit as in claim 14 further including a resistor coupled between the base of the third bipolar transistor and the second rail.

Claim 21

An electronic circuit responsive to (a) a first differential input formed with a first noninverting input and a first inverting input and (b) a second differential input formed with a second noninverting input and a second inverting input, the circuit comprising: a first bipolar transistor having a base responsive to the first noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base responsive to the second noninverting input, a collector coupled to the first rail, and an emitter coupled to the emitter of the first bipolar transistor; a third bipolar transistor having a base, a collector coupled to the emitter of the first bipolar transistor, and an emitter coupled to a second voltage reference rail; a first MOS transistor having a gate electrode responsive to the first inverting input, a drain, and a source; a second MOS transistor having a gate electrode responsive to the second inverting input, a drain, and a source, the first and second MOS transistors being arranged in series such that the drain and the source of one are respectively coupled to the emitter of the first bipolar transistor and to the drain of the other whose source is coupled to the base of the third bipolar transistor; a fourth bipolar transistor having a base responsive to the first inverting input, a collector coupled to the first rail, and an emitter; a fifth bipolar transistor having a base responsive to the second inverting input, a collector coupled to the first rail, and an emitter coupled to the emitter of the fourth bipolar transistor; a sixth bipolar transistor having a base, a collector coupled to the emitter of the fourth bipolar transistor, and an emitter coupled to the second rail; a third MOS transistor having a gate electrode responsive to the first noninverting input, a drain, and a source; and a fourth MOS transistor having a gate electrode responsive to the second noninverting input, a drain, and a source, the third and fourth MOS transistors being arranged in series such that the drain and source of one are respectively coupled to the emitter of the fourth bipolar transistor and to the drain of the other whose source is coupled to the base of the sixth bipolar transistor, a pair of outputs of the circuit being available at nodes respectively coupled to the emitters of the first and fourth bipolar transistors.

Claim 22

An electronic circuit responsive to (a) a first differential input formed with a first noninverting input and a first inverting input and (b) a second differential input formed with a second noninverting input and a second inverting input, the circuit comprising: a first bipolar transistor having a base responsive to the first noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base responsive to the second noninverting input, a collector coupled to the first rail, and an emitter coupled to the emitter of the first bipolar transistor; a third bipolar transistor having a base, a collector coupled to the emitter of the first bipolar transistor, and an emitter coupled to a second voltage reference rail; a first MOS transistor having a gate electrode responsive to the first inverting input, a drain, and a source; a second MOS transistor having a gate electrode responsive to the second inverting input, a drain, and a source, the first and second MOS transistors being arranged in series such that the drain and the source of one are respectively coupled to the emitter of the first bipolar transistor and to the drain of the other whose source is coupled to the base of the third bipolar transistor; a fourth bipolar transistor having a base responsive to the first inverting input, a collector coupled to the first rail, and an emitter; a fifth bipolar transistor having a base responsive to the second inverting input, a collector coupled to the first rail, and an emitter coupled to the emitter of the fourth bipolar transistor; a sixth bipolar transistor having a base, a collector coupled to the emitter of the fourth bipolar transistor, and an emitter coupled to the second rail; a third MOS transistor having a gate electrode responsive to the first noninverting input, a drain, and a source; and a fourth MOS transistor having a gate electrode responsive to the second noninverting input, a drain, and a source, the third and fourth MOS transistors being arranged in series such that the drain and source of one are respectively coupled to the emitter of the fourth bipolar transistor and to the drain of the other whose source is coupled to the base of the sixth bipolar transistor, a pair of outputs of the circuit being available at nodes respectively coupled to the emitters of the first and fourth bipolar transistors.

Claim 23

A circuit as in claim 18 wherein (a) the first noninverting and inverting inputs are substantially synchronous and (b) the second noninverting and inverting inputs are substantially synchronous.

Claim 24

A circuit as in claim 19 wherein the MOS transistors are all of a first MOS type, the bipolar transistors are of a first bipolar type, the first MOS type is nMOS when the first bipolar type is npn, and the first MOS type is pMOS when the first bipolar type is pMOS.

Claim 25

A circuit as in claim 20 further including: a fifth MOS transistor having a gate electrode responsive to the first noninverting input, a drain coupled to the base of the third bipolar transistor, and a source coupled to the second rail; a sixth MOS transistor having a gate electrode responsive to the second noninverting input, a drain coupled to the base of the third bipolar transistor, and a source coupled to the second rail; a seventh MOS transistor having a gate electrode responsive to the first inverting input, a drain coupled to the base of the sixth bipolar transistor, and a source coupled to the second rail; and an eighth MOS transistor having a gate electrode responsive to the second inverting input, a drain coupled to the base of the sixth bipolar transistor, and a source coupled to the second rail, the fifth, sixth, seventh, and eighth MOS transistors being of the first MOS type.

Claim 26

A circuit as in claim 21 further including input means for providing the first and second differential inputs.

Claim 27

A circuit as in claim 20 further including: a first resistor coupled between the base of the third bipolar transistor and the second rail; and a second resistor coupled between the base of the sixth bipolar transistor and the second rail.

Claim 28

An electronic circuit responsive to (a) a first differential input formed with a first noninverting input and a first inverting input and (b) a second differential input formed with a second noninverting input and a second inverting input, the circuit comprising: a first npn transistor having a base responsive to the first noninverting input, a collector coupled to a high voltage reference rail, and an emitter; a second npn transistor having a base responsive to the second noninverting input, a collector coupled to the high rail, and an emitter coupled to the emitter of the first npn transistor; a third npn transistor having a base, a collector coupled to the emitter of the first npn transistor, and an emitter coupled to a low voltage reference rail; a first nMOS transistor having a gate electrode responsive to the first inverting input, a drain, and a source; a second nMOS transistor having a gate electrode responsive to the second inverting input, a drain, and a source, the two nMOS transistors being arranged in series such that the drain and the source of one are respectively coupled to the emitter of the first npn transistor and to the drain of the other whose source is coupled to the base of the third npn transistor; a first pnp transistor having a base responsive to the first inverting input, a collector coupled to the low rail, and an emitter; a second pnp transistor having a base responsive to the second inverting input, a collector coupled to the low rail, and an emitter coupled to the emitter of the first pnp transistor; a third pnp transistor having a base, a collector, coupled to the emitter of the first pnp transistor, and an emitter coupled to the high rail; a first pMOS transistor having a gate electrode responsive to the first noninverting input, a drain, and a source; and a second pMOS transistors having a gate electrode responsive to the second noninverting input, a drain, and a source, the two pMOS transistors being arranged in series such that the drain and the source of one are respectively coupled to the emitter of the first pnp transistor and to the drain of the other whose source is coupled to the base of the third pnp transistor, a pair of outputs of the circuit being available at nodes respectively coupled to the emitters of the first npn and pnp transistors.

Claim 29

An electronic circuit responsive to (a) a first differential input formed with a first noninverting input and a first inverting input and (b) a second differential input formed with a second noninverting input and a second inverting input, the circuit comprising: a first npn transistor having a base responsive to the first noninverting input, a collector coupled to a high voltage reference rail, and an emitter; a second npn transistor having a base responsive to the second noninverting input, a collector coupled to the high rail, and an emitter coupled to the emitter of the first npn transistor; a third npn transistor having a base, a collector coupled to the emitter of the first npn transistor, and an emitter coupled to a low voltage reference rail; a first nMOS transistor having a gate electrode responsive to the first inverting input, a drain, and a source; a second nMOS transistor having a gate electrode responsive to the second inverting input, a drain, and a source, the two nMOS transistors being arranged in series such that the drain and the source of one are respectively coupled to the emitter of the first npn transistor and to the drain of the other whose source is coupled to the base of the third npn transistor; a first pnp transistor having a base responsive to the first inverting input, a collector coupled to the low rail, and an emitter; a second pnp transistor having a base responsive to the second inverting input, a collector coupled to the low rail, and an emitter coupled to the emitter of the first pnp transistor; a third pnp transistor having a base, a collector, coupled to the emitter of the first pnp transistor, and an emitter coupled to the high rail; a first pMOS transistor having a gate electrode responsive to the first noninverting input, a drain, and a source; and a second pMOS transistors having a gate electrode responsive to the second noninverting input, a drain, and a source, the two pMOS transistors being arranged in series such that the drain and the source of one are respectively coupled to the emitter of the first pnp transistor and to the drain of the other whose source is coupled to the base of the third pnp transistor, a pair of outputs of the circuit being available at nodes respectively coupled to the emitters of the first npn and pnp transistors.

Claim 30

A circuit as in claim 24 wherein (a) the first noninverting and inverting inputs are substantially synchronous and (b) the second noninverting and inverting inputs are substantially synchronous.

Claim 31

A circuit as in claim 25 further including: a third nMOS transistor having a gate electrode responsive to the first noninverting input, a drain coupled to the base of the third npn transistor, and a source coupled to the low rail; a fourth nMOS transistor having a gate electrode responsive to the second noninverting input, a drain coupled to the base of the third npn transistor, and a source coupled to the low rail; a third pMOS transistor having a gate electrode responsive to the first inverting input, a drain coupled to the base of the third pnp transistor, and a source coupled to the high rail; and a fourth pMOS transistor having a gate electrode responsive to the second inverting input, a drain coupled to the base of the third pnp transistor, and a source coupled to the high rail.

Claim 32

A circuit as in claim 26 further including input means for providing the first and second differential inputs.

Claim 33

A circuit as in claim 26 further including: a first resistor coupled between the base of the third npn transistor and the low rail. a second resistor coupled between the base of the third pnp transistor and the high rail.

Claim 34

An electronic circuit responsive to a differential input formed with a noninverting input and an inverting input, the circuit comprising: a first bipolar transistor having a base responsive to the noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base responsive to the inverting input, a collector coupled to the first rail, and an emitter; a first MOS transistor having a gate electrode responsive to the inverting input, a drain coupled to the emitter of the first bipolar transistor, and a source coupled to a second voltage reference rail; a second MOS transistor having a gate electrode responsive to the noninverting input, a drain coupled to the emitter of the second bipolar transistor, and a source coupled to the second rail, the first and second MOS transistors being of a first MOS type; a third MOS transistor having a gate electrode coupled to the emitter of the second bipolar transistor, a source coupled to the first rail, and a drain coupled to the emitter of the first bipolar transistor; and a fourth MOS transistor having a gate electrode coupled to the emitter of the first bipolar transistor, a source coupled to the first rail, and a drain coupled to the emitter of the second bipolar transistor, the third and fourth MOS transistors being of a second MOS type opposite to the first MOS type, a pair of outputs of the circuit being available at nodes coupled to the emitters of the bipolar transistors.

Claim 35

An electronic circuit responsive to a differential input formed with a noninverting input and an inverting input, the circuit comprising: a first bipolar transistor having a base responsive to the noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base responsive to the inverting input, a collector coupled to the first rail, and an emitter; a first MOS transistor having a gate electrode responsive to the inverting input, a drain coupled to the emitter of the first bipolar transistor, and a source coupled to a second voltage reference rail; a second MOS transistor having a gate electrode responsive to the noninverting input, a drain coupled to the emitter of the second bipolar transistor, and a source coupled to the second rail, the first and second MOS transistors being of a first MOS type; a third MOS transistor having a gate electrode coupled to the emitter of the second bipolar transistor, a source coupled to the first rail, and a drain coupled to the emitter of the first bipolar transistor; and a fourth MOS transistor having a gate electrode coupled to the emitter of the first bipolar transistor, a source coupled to the first rail, and a drain coupled to the emitter of the second bipolar transistor, the third and fourth MOS transistors being of a second MOS type opposite to the first MOS type, a pair of outputs of the circuit being available at nodes coupled to the emitters of the bipolar transistors.

Claim 36

A circuit as in claim 29 wherein the noninverting and inverting inputs are substantially synchronous.

Claim 37

A circuit as in claim 30 wherein the bipolar transistors are of a first bipolar type, the first MOS type is nMOS when the first bipolar type is npn, and the first MOS type is pMOS when the first bipolar type is pnp.

Claim 38

A circuit as in claim 31 further including input means for providing the differential input.

Claim 39

A circuit as in claim 1 wherein the collectors of the third and fourth bipolar transistors are respectively connected directly to the emitters of the first and second bipolar transistors.

Claim 40

An electronic circuit comprising: input means for providing a differential input formed with a noninverting input and an inverting input; a first bipolar transistor having a base directly coupled to the noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base directly coupled to the inverting input, a collector coupled to the first rail, and an emitter; a third bipolar transistor having a base, a collector directly coupled to the emitter of the first bipolar transistor, and an emitter coupled to a second voltage reference rail; a fourth bipolar transistor having a base, a collector directly coupled to the emitter of the second bipolar transistor, and an emitter coupled to the second rail; a first MOS transistor having a gate electrode directly coupled to the inverting input, a drain coupled to the emitter of the first bipolar transistor, and a source coupled to the base of the third bipolar transistor; and a second MOS transistor having a gate electrode directly coupled to the noninverting input, a drain coupled to the emitter of the second bipolar transistor, and a source coupled to the base of the fourth bipolar transistor, a pair of outputs of the circuit being available at nodes respectively at the emitters of the first and second bipolar transistors.

Claim 41

An electronic circuit comprising: input means for providing a differential input formed with a noninverting input and an inverting input; a first bipolar transistor having a base directly coupled to the noninverting input, a collector coupled to a first voltage reference rail, and an emitter; a second bipolar transistor having a base directly coupled to the inverting input, a collector coupled to the first rail, and an emitter; a third bipolar transistor having a base, a collector directly coupled to the emitter of the first bipolar transistor, and an emitter coupled to a second voltage reference rail; a fourth bipolar transistor having a base, a collector directly coupled to the emitter of the second bipolar transistor, and an emitter coupled to the second rail; a first MOS transistor having a gate electrode directly coupled to the inverting input, a drain coupled to the emitter of the first bipolar transistor, and a source coupled to the base of the third bipolar transistor; and a second MOS transistor having a gate electrode directly coupled to the noninverting input, a drain coupled to the emitter of the second bipolar transistor, and a source coupled to the base of the fourth bipolar transistor, a pair of outputs of the circuit being available at nodes respectively at the emitters of the first and second bipolar transistors.

Claim 42

A circuit as in claim 34 wherein the noninverting and inverting inputs are substantially synchronous.

Claim 43

A circuit as in claim 35 wherein the bipolar transistors are of a first bipolar type, the MOS transistors are of a first MOS type, the first MOS type is nMOS when the first bipolar type is npn, and the first MOS type is pMOS when the first bipolar type is pnp.

Claim 44

A circuit as in claim 36 further including: a third MOS transistor having a gate electrode that receives the noninverting input, a drain coupled to the source of the first MOS transistor, and a source coupled to the second rail; and a fourth MOS transistor having a gate electrode that receives the inverting input, a drain coupled to the source of the second MOS transistor, and a source coupled to the second rail, the third and fourth MOS transistors being of the first MOS type.

Claim 45

A circuit as in claim 36 further including: a first resistor coupled between the source of the first MOS transistor and the second rail; and a second resistor coupled between the source of the second MOS transistor and the second rail.

Claim 46

A circuit as in claim 34 wherein the collectors of the third and fourth bipolar transistors are respectively connected directly to the emitters of the first and second bipolar transistors.