US4804869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BiMOS logical circuit
Assignee: Toshiba Corp
•
Filing: 1987-10-09
•
Granted: 1989-02-14
•
Expires: 2007-10-09
Abstract
Abstract The invention is a BiMOS logical circuit having a reduced number of components and increased operating speed. First and second MOS transistors are provided for, respectively, driving first and second bipolar transistors. The gates of these MOS transistors are, respectively, connected to the bases of the second and first bipolar transistors. The input terminal is connected to the gates of the MOS transistors.
Inventors
- 👤 Masami Masuda
- 👤 Yasumitsu Nozawa
- 👤 Takayuki Kawaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
228 words
A BiMOS logical circuit comprising: a first power source; a first MOS transistor, one end of said first MOS transistor being connected to said first power source; of said a second MOS transistor, one end second MOS transistor being connected to said first power source; a first bipolar transistor, the base of said first bipolar transistor being connected to the other end said first MOS transistor; and a second bipolar transistor, the base of said second bipolar transistor being connected to the other end of said second MOS transistor; a second power source; said first and second bipolar transistors being connected in series at an intermediate node thereof between said second power source and said first power source; the gate of said first MOS transistor and said base of said second bipolar transistor being connected; the gate of said second MOS transistor and said base of said first bipolar transistor being connected; said BiMOS logical circuit further comprising switching means for selectively establishing either a connection between the other end of said first MOS transistor and said second power source or the connection between the other end of said second MOS transistor and said intermediate node on the basis of an input signal delivered to an input terminal, thereby to output an output signal corresponding to said input signal from an output terminal connected to said intermediate node.
Claim 2
Dependent Claim
228 words
A BiMOS logical circuit comprising: a first power source; a first MOS transistor, one end of said first MOS transistor being connected to said first power source; of said a second MOS transistor, one end second MOS transistor being connected to said first power source; a first bipolar transistor, the base of said first bipolar transistor being connected to the other end said first MOS transistor; and a second bipolar transistor, the base of said second bipolar transistor being connected to the other end of said second MOS transistor; a second power source; said first and second bipolar transistors being connected in series at an intermediate node thereof between said second power source and said first power source; the gate of said first MOS transistor and said base of said second bipolar transistor being connected; the gate of said second MOS transistor and said base of said first bipolar transistor being connected; said BiMOS logical circuit further comprising switching means for selectively establishing either a connection between the other end of said first MOS transistor and said second power source or the connection between the other end of said second MOS transistor and said intermediate node on the basis of an input signal delivered to an input terminal, thereby to output an output signal corresponding to said input signal from an output terminal connected to said intermediate node.
Claim 3
Dependent Claim
32 words
A BiMOS logical circuit as set forth in claim 1, wherein said first and second MOS transistors are both NMOS transistors, and said first and second bipolar transistors are both NPN transistors.
Claim 4
Dependent Claim
101 words
A BiMOS logical circuit as set forth in claim 1, wherein said switching means comprises at least one third MOS transistor, one end of said third MOS transistor being connected to said second power source, the other end thereof being connected to said base of said first bipolar transistor, the gate thereof being connected to said input terminal, and at least one fourth MOS transistor, one end of said fourth MOS transistor being connected to said intermediate node, the other end thereof being connected to said base of said second bipolar transistor, the gate thereof being connected to said input terminal.
Claim 5
Dependent Claim
58 words
A BiMOS logical circuit as set forth in claim 3, wherein a plurality of input terminals are provided, said switching means further including a plurality of MOS transistors connected in parallel with said third transistor, each with respective input terminals, and a plurality of MOS transistors connected in series with said fourth transistor, each with respective input terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-14 | 1992-08-15 | 1993-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-14 | 1996-08-15 | 1997-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-14 | 2000-08-15 | 2001-02-14 | $7700.00 | Window Closed / Lapsed |