EP0398808A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Level conversion circuit for converting elc-level signal into ttl-level signal
Assignee: Fujitsu VLSI Ltd
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Filing: 1990-05-16
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Granted: —
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Expires: 2010-05-16
Abstract
Abstract A level conversion circuit includes a level converter (4, 40) and a buffer gate circuit (3, 30, 130, 230). A level converter includes two pairs of P-channel MOS transistors (Tr22, Tr23; Tr24, Tr25). A first input signal is supplied to one (Tr22) of the pair of P-channel MOS transistors and a second input signal is supplied to one (Tr25) of the other pair of P-channel MOS transistors. Each of the first and second input signals are complementary ECL-level signals. The buffer gate circuit includes two BiCMOS circuits. A first output signal from one of the pairs of P-channel MOS transistors is supplied to a gate of an N-channel MOS transistor (Tr15) provided in one of the BiCMOS circuits. A second output signal from the other pair of P-channel MOS transistors is supplied to a gate of an N-channel MOS transistor (Tr17) provided in the other BiCMOS circuit. The first input signal is supplied directly to a gate of a P-channel MOS transistor (Tr14) provided in one of the BiCMOS circuits. The second input signal is supplied directly to a gate of a P-channel MOS transistor (Tr16) provided in the other BiCMOS circuit. A first TTL-level output signal (Q) is output from one of the BiCMOS circuits, and a second TTL-level output signal ( Q ) is output from the other BiCMOS circuit.
Inventors
- 👤 Michiyuki Hirata
- 👤 Chikai Ono
- 👤 Osamu Nomura
- 👤 Toru Fukui
- 👤 Susumu Terawaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 20:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/003; H03K19/00307; H03K19/01; H03K19/013; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/017527
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
455 words
A level conversion circuit comprising: a level converter (4) receiving first and second input signals ((c), (b)) which are complementary ECL-level signals, said level converter including first and second P-channel MOS transistors (Tr22, Tr23) which are connected in series between a first power source (ground) and a second power source (V EE ), and third and fourth P-channel MOS transistors (Tr24, Tr25) which are connected in series between said first power source and said second power source, said first input signal ((c)) being applied to gates of said first and fourth P-channel MOS transistors, said second input signal ((d)) being applied to gates of said second and third P-channel MOS transistors, a first output signal (d) being drawn from a first connection node where said first and second P-channel MOS transistors are connected in series, a second output signal (e) being drawn from a second connection node where said third and fourth P-channel MOS transistors are connected in series; and a buffer gate circuit (3, 30, 130) having a first buffer gate (3a, 30a, 130a) and a second buffer gate (3b, 30b, 130b), said first buffer gate including a fifth P-channel MOS transistor (Tr14) and a first impedance circuit (Z) connected in series between said first power source and a potential less than a potential of said first power source and including a first N-channel MOS transistor (Tr15) and a second impedance circuit (Z) connected in series between said first power source and said potential less than the potential of said first power source, said second input signal being applied directly to a gate of said fifth P-channel MOS transistor, said first output signal being applied to a gate of said first N-channel MOS transistor, said second buffer gate including a sixth P-channel MOS transistor (Tr16) and a third impedance circuit (Z) connected in series between said first power source and a potential less than a potential of said first power source and including a second N-channel MOS transistor (Tr17) and a fourth impedance circuit (Z) connected in series between said first power source and said potential less than the potential of said first power source, said first input signal being applied directly to a gate of said sixth P-channel MOS transistor, said second output signal being applied to a gate of said second N-channel MOS transistor, said buffer gate circuit including first driving means (Tr18, Tr19) for receiving output signals from said fifth P-channel MOS transistor and said first N-channel MOS transistor and for generating a first TTL-level output signal (Q), and second driving means (Tr20, Tr21) for receiving output signals from said sixth P-channel MOS transistor and said second N-channel MOS transistor and for generating a second TTL-level output signal ( Q ).
Claim 2
Dependent Claim
455 words
A level conversion circuit comprising: a level converter (4) receiving first and second input signals ((c), (b)) which are complementary ECL-level signals, said level converter including first and second P-channel MOS transistors (Tr22, Tr23) which are connected in series between a first power source (ground) and a second power source (V EE ), and third and fourth P-channel MOS transistors (Tr24, Tr25) which are connected in series between said first power source and said second power source, said first input signal ((c)) being applied to gates of said first and fourth P-channel MOS transistors, said second input signal ((d)) being applied to gates of said second and third P-channel MOS transistors, a first output signal (d) being drawn from a first connection node where said first and second P-channel MOS transistors are connected in series, a second output signal (e) being drawn from a second connection node where said third and fourth P-channel MOS transistors are connected in series; and a buffer gate circuit (3, 30, 130) having a first buffer gate (3a, 30a, 130a) and a second buffer gate (3b, 30b, 130b), said first buffer gate including a fifth P-channel MOS transistor (Tr14) and a first impedance circuit (Z) connected in series between said first power source and a potential less than a potential of said first power source and including a first N-channel MOS transistor (Tr15) and a second impedance circuit (Z) connected in series between said first power source and said potential less than the potential of said first power source, said second input signal being applied directly to a gate of said fifth P-channel MOS transistor, said first output signal being applied to a gate of said first N-channel MOS transistor, said second buffer gate including a sixth P-channel MOS transistor (Tr16) and a third impedance circuit (Z) connected in series between said first power source and a potential less than a potential of said first power source and including a second N-channel MOS transistor (Tr17) and a fourth impedance circuit (Z) connected in series between said first power source and said potential less than the potential of said first power source, said first input signal being applied directly to a gate of said sixth P-channel MOS transistor, said second output signal being applied to a gate of said second N-channel MOS transistor, said buffer gate circuit including first driving means (Tr18, Tr19) for receiving output signals from said fifth P-channel MOS transistor and said first N-channel MOS transistor and for generating a first TTL-level output signal (Q), and second driving means (Tr20, Tr21) for receiving output signals from said sixth P-channel MOS transistor and said second N-channel MOS transistor and for generating a second TTL-level output signal ( Q ).
Claim 3
Dependent Claim
234 words
A level conversion circuit as claimed in claim 1, characterized in that: each of said first, second, third and fourth impedance circuits comprises an N-channel MOS transistor (Tr26, Tr27, Tr28, Tr29); said N-channel MOS transistor (Tr26) of said first impedance circuit having a gate supplied with said first output signal from said first connection node, a drain connected to a drain of said fifth P-channel MOS transistor (Tr14) and a source connected to said second power source; said N-channel MOS transistor (Tr27) of said second impedance circuit having a gate connected to a drain of said first N-channel MOS transistor (Tr15) through which said first TTL-level output signal is drawn, a drain connected to a source of said first N-channel MOS transistor (Tr15) and a source connected to said second power source; said N-channel MOS transistor (Tr28) of said third impedance circuit having a gate supplied with said second output signal (e) from said second connection node, a drain connected to a drain of said sixth P-channel MOS transistor (Tr16) and a source connected to said second power source; and said N-channel MOS transistor (Tr29) of said fourth impedance circuit has a gate connected to a drain of said second N-channel MOS transistor (Tr17) through which said second TTL-level output signal is drawn, a drain connected to a source of said second N-channel MOS transistor (Tr17) and a source connected to said second power.
Claim 4
Dependent Claim
65 words
A level conversion circuit as claimed in claim 1, characterized in that: said first output signal (d) from said first connection node is supplied to the gate of the N-channel MOS transistor (Tr29) of said fourth impedance circuit; and said second output signal (e) from said second connection node is applied to the gate of the N-channel MOS transistor (Tr27) of said second impedance circuit.
Claim 5
Dependent Claim
128 words
A level conversion circuit as claimed in claim 1, characterized in that: said first P-channel MOS transistor (Tr22) has a source connected to said first power source and a drain connected to the gate of said first N-channel MOS transistor (Tr15); said second P-channel MOS transistor (Tr23) has a source connected to the drain of said first P-channel MOS transistor and a drain connected to said second power source; said third P-channel MOS transistor (Tr24) has a source connected to said first power source and a drain connected to the gate of said second N-channel MOS transistor (Tr17); and said fourth P-channel MOS transistor (Tr25) has a source connected to the drain of said third P-channel MOS transistor (Tr24) and a drain connected to said second power source.
Claim 6
Dependent Claim
89 words
A level conversion circuit as claimed in claim 2, characterized in that said first buffer gate (30a) comprises a first diode (D1) having an anode connected to the drain of said first N-channel MOS transistor (Tr15) and a cathode connected to a drain of said fifth P-channel MOS transistor (Tr14), and said second buffer gate (30b) comprises a second diode (D2) having an anode connected to the drain of said second N-channel MOS transistor (Tr17) and a cathode connected to a drain of said sixth P-channel MOS transistor (Tr16).
Claim 7
Dependent Claim
89 words
A level conversion circuit as claimed in claim 3, characterized in that said first buffer gate (130a) comprises a first diode (D1) having an anode connected to the drain of said first N-channel MOS transistor (Tr15) and a cathode connected to a drain of said fifth P-channel MOS transistor (Tr14), and said second buffer gate (130b) comprises a second diode (D2) having an anode connected to the drain of said second N-channel MOS transistor (Tr17) and a cathode connected to a drain of said sixth P-channel MOS transistor (Tr16).
Claim 8
Dependent Claim
239 words
A level conversion circuit as claimed in claim 1, characterized in that: said first driving means comprises a first bipolar transistor (Tr18) having a collector connected to said first power source, a base connected to a drain of said fifth P-channel MOS transistor (Tr14) and said first impedance circuit and an emitter, and a second bipolar transistor (Tr19) having a collector connected to the emitter of said first bipolar transistor, a base connected to a source of said first N-channel MOS transistor (Tr15) and an emitter connected to said second power source; said first TTL-level output signal (Q) is drawn from a connection node where the emitter of said first bipolar transistor (Tr18) is connected to the collector of said second bipolar transistor (Tr19); said second driving means comprises a third bipolar transistor (Tr20) having a collector connected to said first power source, a base connected to a drain of said sixth P-channel MOS transistor (Tr16) and said third impedance circuit and an emitter, and a fourth bipolar transistor (Tr21) having a collector connected to the emitter of said third bipolar transistor, a base connected to a source of said second N-channel MOS transistor (Tr17) and an emitter connected to said second power source; and said second TTL-level output signal ( Q ) is drawn from a connection node where the emitter of said third bipolar transistor (Tr20) is connected to the collector of said fourth bipolar transistor (Tr21).
Claim 9
Dependent Claim
434 words
A level conversion circuit comprising: a level converter (40) receiving first and second input signals ((c), (b)) which are complementary ECL-level signals, said level converter including first and second P-channel MOS transistors (Tr14, Tr23) which are connected in series between a first power source (ground) and a second power source (V EE ), and third and fourth P-channel MOS transistors (Tr16, Tr25) which are connected in series between said first power source and said second power source, said first input signal ((c)) being applied to gates of said first and fourth P-channel MOS transistors, said second input signal ((b)) being applied to gates of said second and third P-channel MOS transistors, a first output signal ((d)) being drawn from a first connection node where said first and second P-channel MOS transistors are connected in series, a second output signal ((e)) being drawn from a second connection node where said third and fourth P-channel MOS transistors are connected in series; and a buffer gate circuit (230) having a first buffer gate (230a) and a second buffer gate (230b), said first buffer gate (230a) including said first P-channel MOS transistor (Tr14) and a first N-channel MOS transistor (Tr26) connected in series between said first and second power sources, said first buffer gate including a second N-channel MOS transistor (Tr15) and a third N-channel MOS transistor (Tr27) connected in series between said first and second power sources, said second buffer gate (230b) including said third P-channel MOS transistor (Tr16) and a fourth N-channel MOS transistor (Tr28) connected in series between said first and second power sources, said second buffer gate including a fifth N-channel MOS transistor (Tr17) and a sixth N-channel MOS transistor (Tr29) connected in series between said first and second power sources, said first output signal from said first connection node being applied to gates of said third, fourth and fifth N-channel MOS transistors (Tr27, Tr28, Tr29), said second output signal from said second connection node being applied to gates of said first, third and sixth N-channel MOS transistors (Tr26, Tr27, Tr29), said buffer gate circuit (230) including first driving means (Tr18, Tr19) for receiving two output signals respectively supplied from said first connection node and a connection node where said second and third N-channel MOS transistors are connected in series and for generating a first TTL-level output signal (Q), and second driving means (Tr20, Tr21) for receiving two output signals respectively supplied from said second connection node and a connection node where said fifth and sixth N-channel MOS transistors are connected in series and for generating a second TTL-level output signal ( Q ).
Claim 10
Dependent Claim
434 words
A level conversion circuit comprising: a level converter (40) receiving first and second input signals ((c), (b)) which are complementary ECL-level signals, said level converter including first and second P-channel MOS transistors (Tr14, Tr23) which are connected in series between a first power source (ground) and a second power source (V EE ), and third and fourth P-channel MOS transistors (Tr16, Tr25) which are connected in series between said first power source and said second power source, said first input signal ((c)) being applied to gates of said first and fourth P-channel MOS transistors, said second input signal ((b)) being applied to gates of said second and third P-channel MOS transistors, a first output signal ((d)) being drawn from a first connection node where said first and second P-channel MOS transistors are connected in series, a second output signal ((e)) being drawn from a second connection node where said third and fourth P-channel MOS transistors are connected in series; and a buffer gate circuit (230) having a first buffer gate (230a) and a second buffer gate (230b), said first buffer gate (230a) including said first P-channel MOS transistor (Tr14) and a first N-channel MOS transistor (Tr26) connected in series between said first and second power sources, said first buffer gate including a second N-channel MOS transistor (Tr15) and a third N-channel MOS transistor (Tr27) connected in series between said first and second power sources, said second buffer gate (230b) including said third P-channel MOS transistor (Tr16) and a fourth N-channel MOS transistor (Tr28) connected in series between said first and second power sources, said second buffer gate including a fifth N-channel MOS transistor (Tr17) and a sixth N-channel MOS transistor (Tr29) connected in series between said first and second power sources, said first output signal from said first connection node being applied to gates of said third, fourth and fifth N-channel MOS transistors (Tr27, Tr28, Tr29), said second output signal from said second connection node being applied to gates of said first, third and sixth N-channel MOS transistors (Tr26, Tr27, Tr29), said buffer gate circuit (230) including first driving means (Tr18, Tr19) for receiving two output signals respectively supplied from said first connection node and a connection node where said second and third N-channel MOS transistors are connected in series and for generating a first TTL-level output signal (Q), and second driving means (Tr20, Tr21) for receiving two output signals respectively supplied from said second connection node and a connection node where said fifth and sixth N-channel MOS transistors are connected in series and for generating a second TTL-level output signal ( Q ).
Claim 11
Dependent Claim
220 words
A level conversion circuit as claimed in claim 8, characterized in that: said first driving means (230a) comprises a first bipolar transistor (Tr18) having a collector connected to said first power source, a base connected to said first connection node and an emitter, and a second bipolar transistor (Tr19) having a collector connected to the emitter of said first bipolar transistor, a base connected to a source of said second N-channel MOS transistor (Tr15) and an emitter connected to said second power source; said first TTL-level output signal (Q) is drawn from a connection node where the emitter of said first bipolar transistor (Tr18) is connected to the collector of said second bipolar transistor (Tr19); said second driving means comprises a third bipolar transistor (Tr20) having a collector connected to said first power source, a base connected to said second connection node and an emitter, and a fourth bipolar transistor (Tr21) having a collector connected to the emitter of said third bipolar transistor, a base connected to a source of said fifth N-channel MOS transistor (Tr17) and an emitter connected to said second power source; and said second TTL-level output signal ( Q ) is drawn from a connection node where the emitter of said third bipolar transistor (Tr20) is connected to the collector of said fourth bipolar transistor (Tr21).
Claim 12
Dependent Claim
83 words
A level conversion circuit as claimed in claim 9, characterized in that: said first buffer gate (230a) comprises a first diode (D1) having an anode connected to the emitter of said first bipolar transistor (Tr18) and a cathode connected to the base of said first bipolar transistor; and said second buffer gate (230b) comprises a second diode (D2) having an anode connected to the emitter of said third bipolar transistor (Tr20) and a cathode connected to the base of said third bipolar transistor.
Claim 13
Dependent Claim
279 words
A level conversion circuit comprising: a level converter receiving first and second input signals ((c), (b)) which are complementary ECL-level signals, said level converter including first and second P-channel MOS transistors (Tr22, Tr23; Tr24, Tr25) which are connected in series between a first power source (ground) and a second power source (V EE ), said first input signal ((c)) being applied to a gate of said first P-channel MOS transistor (Tr22; Tr24), said second input signal being applied to a gate of said second P-channel MOS transistor, an output signal ((d); (e)) being drawn from a connection node where said first and second P-MOS transistors are connected in series; and a buffer gate circuit (3, 30, 130) having a buffer gate (3a, 30a, 130a; 3b, 30b; 130b), said buffer gate including a third P-channel MOS transistor (Tr14; Tr16) and a first impedance (Z) which are connected in series between said first power source and a predetermined potential less than a potential of said first power source, said first buffer gate including an N-channel MOS transistor (Tr15; Tr17) and a second impedance circuit (Z) which are connected in series between said first power source and a potential less than the potential of said first power source, said third P-channel MOS transistor (Tr14; Tr16) having a gate to which said second input signal is directly applied, and said N-channel MOS transistor having a gate to which said output signal from said connection node is applied, said buffer gate circuit including driving means (Tr18, Tr19; Tr20, Tr21) for receiving output signals from said third P-channel MOS transistor and said N-channel MOS transistor and for generating a TTL-level output signal (Q, Q ).
Claim 14
Dependent Claim
279 words
A level conversion circuit comprising: a level converter receiving first and second input signals ((c), (b)) which are complementary ECL-level signals, said level converter including first and second P-channel MOS transistors (Tr22, Tr23; Tr24, Tr25) which are connected in series between a first power source (ground) and a second power source (V EE ), said first input signal ((c)) being applied to a gate of said first P-channel MOS transistor (Tr22; Tr24), said second input signal being applied to a gate of said second P-channel MOS transistor, an output signal ((d); (e)) being drawn from a connection node where said first and second P-MOS transistors are connected in series; and a buffer gate circuit (3, 30, 130) having a buffer gate (3a, 30a, 130a; 3b, 30b; 130b), said buffer gate including a third P-channel MOS transistor (Tr14; Tr16) and a first impedance (Z) which are connected in series between said first power source and a predetermined potential less than a potential of said first power source, said first buffer gate including an N-channel MOS transistor (Tr15; Tr17) and a second impedance circuit (Z) which are connected in series between said first power source and a potential less than the potential of said first power source, said third P-channel MOS transistor (Tr14; Tr16) having a gate to which said second input signal is directly applied, and said N-channel MOS transistor having a gate to which said output signal from said connection node is applied, said buffer gate circuit including driving means (Tr18, Tr19; Tr20, Tr21) for receiving output signals from said third P-channel MOS transistor and said N-channel MOS transistor and for generating a TTL-level output signal (Q, Q ).
Claim 15
Dependent Claim
127 words
A level conversion circuit as claimed in claim 11, characterized in that: each of said first and second impedance circuits comprises an N-channel MOS transistor (Tr26, Tr27; Tr28, Tr29); the N-channel MOS transistor (Tr26; Tr28) of said first impedance circuit having a gate to which said output signal from said node is applied, a drain connected to a drain of said third P-channel MOS transistor and a source connected to said second power source; and the N-channel MOS transistor (Tr27; Tr29) of said second impedance circuit having a gate coupled to the drain of said third P-channel MOS transistor, a drain connected to a source of said N-channel MOS transistor having the gate connected to said connection node and a source connected to said second power source.
Claim 16
Dependent Claim
50 words
A level conversion circuit as claimed in claim 12, characterized in that said buffer gate includes a diode (D1; D2) having an anode connected to the gate of said N-channel MOS transistor of said second impedance circuit and a cathode connected to the drain of said third P-channel MOS transistor.
References Cited (Backward Citations)
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