US4638186A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BIMOS logic gate
Assignee: NXP USA Inc
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Filing: 1985-12-02
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Granted: 1987-01-20
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Expires: 2005-12-02
Abstract
Abstract A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A first MOS transistor circuit is coupled between an input terminal and the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between the input terminal and the upper transistor for biasing the upper transistor. A third circuit is coupled between the input terminal and the lower transistor and is responsive to the output terminal for biasing the lower transistor.
Inventors
- 👤 Kevin L. McLaughlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/01; H03K19/013; H03K19/0136
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
158 words
A circuit comprising: a first supply voltage terminal; a second supply voltage terminal; an input terminal; an output terminal; a first bipolar transistor having its collector-emitter current path coupled between said first supply voltage terminal and said output terminal; a second bipolar trnsistor having its collector-emitter current path coupled between said output terminal and said second supply voltage terminal; first means coupled between said first and second supply voltage terminals and coupled to said input terminal and a base of said first transistor for providing a voltage for biasing said first transistor, said first means providing a high impedance to said input terminal; second means coupled between said output terminal and a base of said second bipolar transistor and coupled to said input terminal for biasing said second transistor; and third means coupled between said input terminal and said base of said second bipolar transistor and coupled to said output terminal for further biasing said second bipolar transistor.
Claim 2
Dependent Claim
158 words
A circuit comprising: a first supply voltage terminal; a second supply voltage terminal; an input terminal; an output terminal; a first bipolar transistor having its collector-emitter current path coupled between said first supply voltage terminal and said output terminal; a second bipolar trnsistor having its collector-emitter current path coupled between said output terminal and said second supply voltage terminal; first means coupled between said first and second supply voltage terminals and coupled to said input terminal and a base of said first transistor for providing a voltage for biasing said first transistor, said first means providing a high impedance to said input terminal; second means coupled between said output terminal and a base of said second bipolar transistor and coupled to said input terminal for biasing said second transistor; and third means coupled between said input terminal and said base of said second bipolar transistor and coupled to said output terminal for further biasing said second bipolar transistor.
Claim 3
Dependent Claim
79 words
The circuit according to claim 1 wherein said first means comprises: a first P-channel MOS transistor having a source coupled to said first supply voltage terminal, a gate coupled to said input terminal, and a drain coupled to said base of said first bipolar transistor; a first N-channel MOS transistor having a source coupled to said second supply voltage terminal, a gate coupled to said input terminal, and a drain coupled to said base of said first bipolar transistor.
Claim 4
Dependent Claim
83 words
The circuit according to claim 2 wherein said second means comprises: a second N-channel MOS transistor having a drain coupled to said output terminal, a source coupled to a base of said second bipolar transistor, and a gate coupled to said input terminal; and a third N-channel MOS transistor having a drain coupled to the base of said second bipolar transistor, a source coupled to said second supply voltage terminal, and a gate coupled to said drain of said first P-channel MOS transistor.
Claim 5
Dependent Claim
61 words
The circuit according to claim 2 wherein said second means comprises: a second N-channel MOS transistor having a drain coupled to said output terminal, a source coupled to a base of said second bipolar transistor, and a gate coupled to said input terminal; and a resistor coupled between said base of said second bipolar transistor and said second supply voltage terminal.
Claim 6
Dependent Claim
71 words
The circuit according to claim 2 further comprising: a third bipolar transistor coupled between said first supply voltage terminal and said base of said first bipolar transistor and having a base coupled to said drain of said first P-channel MOS transistor; and a third N-channel MOS transistor coupled between said base of said first bipolar transistor and said second supply voltage terminal, and having a gate coupled to said input terminal.
Claim 7
Dependent Claim
43 words
The circuit according to claim 1 wherein said third means comprises a first N-channel MOS transistor having a source coupled to said input terminal, a drain coupled to said base of said second bipolar transistor, and a gate coupled to said output terminal.
References Cited (Backward Citations)
US4425516A
Cited
EP0145004A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-19 | 1990-07-21 | 1991-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-19 | 1994-07-21 | 1995-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-19 | 1998-07-21 | 1999-01-20 | $7700.00 | Window Closed / Lapsed |