Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture

Claim 1

A matrix of EPROM memory cells comprising a semiconductor substrate, source lines and drain lines parallel to and alternated with one another on said substrate, floating gate areas interposed in a checkerboard pattern between said source lines and said drain lines, control gate lines parallel to one another and perpendicular to said source and drain lines and superimposed to and aligned with said floating gate areas with a dielectric being interposed therebetween, and field oxide areas formed on said substrate in spaces between said source and drain lines and between said control gate lines and aligned with said floating gate areas in a direction parallel to said source and drain lines, said field oxide areas further extending below lateral portions of the floating gate areas and superimposed portions of the control gate lines in said parallel direction so as to provide each floating gate area and corresponding control gate line with a pair of symmetrical lateral fins superimposed to respective field oxide areas, and said field oxide areas are aligned with said floating gate areas and said source and drain lines in a direction perpendicular to said control gate lines.