US4897815A
Expired / Lapsed
US
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High-speed write type nonvolatile semiconductor memory
Assignee: Toshiba Corp
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Filing: 1987-09-15
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Granted: 1990-01-30
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Expires: 2007-09-15
Abstract
Abstract A nonvolatile semiconductor memory of this invention is obtained by dividing a memory cell array in which EPROM cells are provided in a matrix form and a write circuit into a plurality of blocks, commonly connecting sources of cell transistors in each block of the memory cell array, and connecting the common source of each block to a ground node through a corresponding resistive component.
Inventors
- 👤 Sumio Tanaka
- 👤 Shinji Saito
- 👤 Shigeru Atsumi
- 👤 Nobuaki Ohtsuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:27
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
88 words
A nonvolatile semiconductor memory comprising: a memory cell array divided into a plurality of blocks, each of said divided blocks including data memory cell MOS transistors arranged in a matrix form and write circuits for sending write data to said cell MOS transistors; and resistive elements, each resistive element included in only one of the blocks in said plurality of blocks, for connecting sources of said cell MOS transistors commonly connected in each of said plurality of blocks to one end of a power circuit of said memory.
Claim 2
Dependent Claim
88 words
A nonvolatile semiconductor memory comprising: a memory cell array divided into a plurality of blocks, each of said divided blocks including data memory cell MOS transistors arranged in a matrix form and write circuits for sending write data to said cell MOS transistors; and resistive elements, each resistive element included in only one of the blocks in said plurality of blocks, for connecting sources of said cell MOS transistors commonly connected in each of said plurality of blocks to one end of a power circuit of said memory.
Claim 3
Dependent Claim
41 words
A memory according to claim 1, wherein each of said cell MOS transistors include a control gage electrode having a gate width and wherein a width of each of said resistive elements corresponds to said width of said control gate electrode.
Claim 4
Dependent Claim
53 words
A memory according to claim 1, wherein each of said cell MOS transistors includes a control gate electrode and a channel having a channel width, and wherein each said resistive element has a width corresponding to said channel width and is formed of the same material as that of said control gate electrode.
Claim 5
Dependent Claim
74 words
A memory according to claim 1, wherein each of said cell MOS transistors includes a channel having a channel width, and wherein a resistance of each said resistive element is selected so that a range between upper and lower limits of a channel width of said cell MOS transistors required to set a value of a data write time with respect to said cell MOS transistors smaller than a predetermined value in substantially maximized.
Claim 6
Dependent Claim
31 words
A memory according to claim 1, further comprising switching elements provided electrically parallel to said resistive elements to be turned on when data is read out from said cell MOS transistors.
Claim 7
Dependent Claim
118 words
A nonvolatile semiconductor memory comprising: a memory cell array divided into at least two blocks, each of said divided blocks including data memory cell MOS transistors; and resistive components, respectively provided in said blocks, for connecting sources of said cell MOS transistors commonly connected in each of said blocks to one end of a power source circuit of memory, wherein each of said cell MOS transistors includes a control gate electrode having a gate width, wherein each of said resistive components has a width corresponding to said gate width of said control gate electrodes of said cell MOS transistors and is formed of the same material as that of said control gate electrodes of said cell MOS transistors.
Claim 8
Dependent Claim
118 words
A nonvolatile semiconductor memory comprising: a memory cell array divided into at least two blocks, each of said divided blocks including data memory cell MOS transistors; and resistive components, respectively provided in said blocks, for connecting sources of said cell MOS transistors commonly connected in each of said blocks to one end of a power source circuit of memory, wherein each of said cell MOS transistors includes a control gate electrode having a gate width, wherein each of said resistive components has a width corresponding to said gate width of said control gate electrodes of said cell MOS transistors and is formed of the same material as that of said control gate electrodes of said cell MOS transistors.
Claim 9
Dependent Claim
30 words
A memory according to claim 6, wherein each said resistive component has a width substantially the same as a width of said control gate electrodes of said cell MOS transistors.
Claim 10
Dependent Claim
74 words
A memory according to claim 6, wherein each of said cell MOS transistors includes a channel having a channel width, and wherein a resistance of each said resistive component is selected so that a range between upper and lower limits of a channel width of said cell MOS transistors required to set a value of a data write time with respect to said cell MOS transistors smaller than a predetermined value is substantially maximized.
Claim 11
Dependent Claim
31 words
A memory according to claim 6, further comprising: switching elements provided electrically parallel to said resistive elements to be turned on when data is read out from said cell MOS transistors.
Claim 12
Dependent Claim
31 words
A memory according to claim 7, further comprising: switching elements provided electrically parallel to said resistive elements to be turned on when data is read out from said cell MOS transistors.
Claim 13
Dependent Claim
31 words
A memory according to claim 8, further comprising: switching elements provided electrically parallel to said resistive elements to be turned on when data is read out from said cell MOS transistors.
Claim 14
Dependent Claim
117 words
A nonvolatile semiconductor memory comprising: a memory cell array divided into a plurality of blocks, each of said divided blocks including data memory cell MOS transistors arranged in a matrix form and write circuits for sending write data to said cell MOS transistors; and resistive elements, in said plurality of blocks, for connecting sources of said cell MOS transistors commonly connected in each of said plurality of blocks to one end of a power circuit of said memory, wherein each said resistive element has a width corresponding to a channel width of said cell MOS transistors and is formed of the same material as that of a control gate electrode of each of said cell MOS transistors.
Claim 15
Dependent Claim
117 words
A nonvolatile semiconductor memory comprising: a memory cell array divided into a plurality of blocks, each of said divided blocks including data memory cell MOS transistors arranged in a matrix form and write circuits for sending write data to said cell MOS transistors; and resistive elements, in said plurality of blocks, for connecting sources of said cell MOS transistors commonly connected in each of said plurality of blocks to one end of a power circuit of said memory, wherein each said resistive element has a width corresponding to a channel width of said cell MOS transistors and is formed of the same material as that of a control gate electrode of each of said cell MOS transistors.
Claim 16
Dependent Claim
24 words
A memory according to claim 12, wherein a width of each of said resistive elements corresponds to a width of said control gate electrodes.
Claim 17
Dependent Claim
59 words
A memory according to claim 12, wherein a resistance of each said resistive element is selected so that a range between upper and lower limits of a channel width of said cell MOS transistors required to set a value of a data write time with respect to said cell MOS transistors smaller than a predetermined value is substantially maximized.
Claim 18
Dependent Claim
31 words
A memory according to claim 12, further comprising switching elements provided electrically parallel to said resistive elements to be turned on when data is read out from said cell MOS transistors.
Claim 19
Dependent Claim
131 words
A nonvolatile semiconductor memory comprising: a memory cell array divided into a plurality of blocks, each of said divided blocks including data memory cell MOS transistors arranged in a matrix form and write circuits for sending write data to said cell MOS transistors; and resistive elements, in said plurality of blocks, for connecting sources of said cell MOS transistors commonly connected in each of said plurality of blocks to one end of a power circuit of said memory, wherein a resistance of each said resistive element is selected so that a range between upper and lower limits of a channel width of said cell MOS transistors required to set a value of a data write time with respect to said cell MOS transistors smaller than a predetermined value is substantially maximized.
Claim 20
Dependent Claim
131 words
A nonvolatile semiconductor memory comprising: a memory cell array divided into a plurality of blocks, each of said divided blocks including data memory cell MOS transistors arranged in a matrix form and write circuits for sending write data to said cell MOS transistors; and resistive elements, in said plurality of blocks, for connecting sources of said cell MOS transistors commonly connected in each of said plurality of blocks to one end of a power circuit of said memory, wherein a resistance of each said resistive element is selected so that a range between upper and lower limits of a channel width of said cell MOS transistors required to set a value of a data write time with respect to said cell MOS transistors smaller than a predetermined value is substantially maximized.
Claim 21
Dependent Claim
31 words
A memory according to claim 16, wherein a width of each of said resistive elements corresponds to a width of a control gate electrode of each of said cell MOS transistors.
Claim 22
Dependent Claim
45 words
A memory according to claim 16, wherein each said resistive element has a width corresponding to a channel width of said cell MOS transistors and is formed of the same material as that of a control gate electrode of each of said cell MOS transistors.
Claim 23
Dependent Claim
31 words
A memory according to claim 16, further comprising switching elements provided electrically parallel to said resistive elements to be turned on when data is read out from said cell MOS transistors.
Claim 24
Dependent Claim
103 words
A nonvolatile semiconductor memory comprising: a memory cell array divided into a plurality of blocks, each of said divided blocks including data memory cell MOS transistors arranged in a matrix form and write circuits for sending write data to said cell MOS transistors; resistive elements, independently provided in said plurality of blocks, for connecting sources of said cell MOS transistors commonly connected in each of said plurality of blocks to one end of a power circuit of said memory; and switching elements provided electrically parallel to said resistive elements to be turned on when data is read out from said cell MOS transistors.
Claim 25
Dependent Claim
103 words
A nonvolatile semiconductor memory comprising: a memory cell array divided into a plurality of blocks, each of said divided blocks including data memory cell MOS transistors arranged in a matrix form and write circuits for sending write data to said cell MOS transistors; resistive elements, independently provided in said plurality of blocks, for connecting sources of said cell MOS transistors commonly connected in each of said plurality of blocks to one end of a power circuit of said memory; and switching elements provided electrically parallel to said resistive elements to be turned on when data is read out from said cell MOS transistors.
Claim 26
Dependent Claim
31 words
A memory according to claim 20, wherein a width of each of said resistive elements corresponds to a width of a control gate electrode of each of said cell MOS transistors.
Claim 27
Dependent Claim
45 words
A memory according to claim 20 wherein each said resistive element has a width corresponding to a channel width of said cell MOS transistors and is formed of the same material as that of a control gate electrode of each of said cell MOS transistors.
Claim 28
Dependent Claim
59 words
A memory according to claim 20, wherein a resistance of each said resistive element is selected so that a range between upper and lower limits of a channel width of said cell MOS transistors required to set a value of a data write time with respect to said cell MOS transistors smaller than a predetermined value is substantially maximized.
References Cited (Backward Citations)
US3618052A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-29 | 1993-07-31 | 1994-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-29 | 1997-07-31 | 1998-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-29 | 2001-07-31 | 2002-01-30 | $7700.00 | Window Closed / Lapsed |