US4905062A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Planar famos transistor with trench isolation
Assignee: Texas Instruments Inc
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Filing: 1989-02-17
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Granted: 1990-02-27
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Expires: 2009-02-17
Abstract
Abstract A sealed gate FAMOS transistor (28) disposes a thermal oxide layer (40) about the floating gate (34) in order to isolate the floating gate (34) from the planar isolating regions (44) between floating gates (34). Trench isolating regions (54) are provided between control gates (50) to enhance programmability of the sealed gate FAMOS transistor (28).
Inventors
- 👤 Agerico L. Esquivel
- 👤 Allan T. Mitchell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:44
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
175 words
A non-volatile memory cell array comprising: a semiconductor substrate; a plurality of doped bit line regions formed in said substrate; a plurality of floating gates overlying said substrate, each having a top surface, and each of said floating gates disposed between a pair of bit line regions and defining a channel region in said substrate lying under said floating gate and between said bit line regions; a plurality of dielectric structures, each disposed over one of said bit line regions and having a top surface substantially even with the top surfaces of said floating gates; a plurality of control gages each overlying a plurality of floating gates and overlying a plurality of dielectric structures and bit line regions therebelow; and a plurality of trench isolation regions each disposed between adjacent ones of said floating gates disposed between the same pair of bit line regions, and between adjacent ones of said dielectric structures overlying said pair of bit line regions, said trench isolation regions extending into said substrate substantially below the surface of said channel regions.
Claim 2
Dependent Claim
175 words
A non-volatile memory cell array comprising: a semiconductor substrate; a plurality of doped bit line regions formed in said substrate; a plurality of floating gates overlying said substrate, each having a top surface, and each of said floating gates disposed between a pair of bit line regions and defining a channel region in said substrate lying under said floating gate and between said bit line regions; a plurality of dielectric structures, each disposed over one of said bit line regions and having a top surface substantially even with the top surfaces of said floating gates; a plurality of control gages each overlying a plurality of floating gates and overlying a plurality of dielectric structures and bit line regions therebelow; and a plurality of trench isolation regions each disposed between adjacent ones of said floating gates disposed between the same pair of bit line regions, and between adjacent ones of said dielectric structures overlying said pair of bit line regions, said trench isolation regions extending into said substrate substantially below the surface of said channel regions.
Claim 3
Dependent Claim
40 words
The memory cell array of claim 1 wherein each of said floating gates have sides insulated by a thermal silicon oxide; and wherein said dielectric structures each comprise a deposited dielectric disposed between the insulated sides of adjacent floating gates.
Claim 4
Dependent Claim
16 words
The memory cell array of claim 2 wherein said deposited dielectric comprises a deposited silicon oxide.
Claim 5
Dependent Claim
32 words
The memory cell array of claim 1 wherein said trench isolation regions each comprise a second dielectric structure disposed within said substrate and separated from said substrate by a sidewall oxide layer.
Claim 6
Dependent Claim
17 words
The memory array of claim 1 and further comprising channel stop regions underlying said trench isolation regions.
Claim 7
Dependent Claim
23 words
The memory array of claim 1 wherein said floating gates each overlie a portion of the pair of bit line regions adjacent thereto.
Claim 8
Dependent Claim
14 words
The memory array of claim 1 wherein said memory cells comprise EPROM memory cells.
Claim 9
Dependent Claim
14 words
The memory array of claim 1 wherein said memory cells comprise EEPROM memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-26 | 1993-08-28 | 1994-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-26 | 1997-08-28 | 1998-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-26 | 2001-08-28 | 2002-02-27 | $7700.00 | Window Closed / Lapsed |