Non-volatile semiconductor memory device

Claim 2

A semiconductor memory device comprising a plurality of memory cells, a plurality of row lines, each of which is coupled to at least one of said memory cells, at least one column line coupled to each memory cell, an address decoder selecting one of row lines and one column line to designate one of memory cells, a terminal at which a writing voltage is supplied, a writing circuit coupled between said row lines and said terminal, said writing circuit having a plurality of switching circuits, one end of each switching circuit being coupled in common to said terminal, the other end of each switching circuit being coupled to the respective row lines, and a control circuit coupled to said writing circuit, only one switching circuit coupled to a row line selected by said address decoder being turned on by said control circuit.

Claim 3

A semiconductor memory device as claimed in Claim 1, in which each of said switching circuit has a plurality of enhancement type transistors and a plurality of depletion type transistors which are serially connected in a predetermined order between each row line and said terminal, and said control circuit turns off at least one transistor in all switching circuits except for the switching circuit coupled to the selected row line.

Claim 4

A semiconductor memory device as claimed in Claim 1, further comprising means for electrically separating all switching circuits from the row lines in a data read operation.

Claim 5

A semiconductor memory device as claimed in Claim 3, in which said separating means is responsive to a read control signal applied to the semiconductor memory.

Claim 6

A semiconductor memory device as claimed in Claim 2, in which at least one depletion type transistor is replaced to an enhancement type transistor whose drain electrode and source electrode are electrically shorted each other.

Claim 7

A semiconductor memory device as claimed in Claim 2, in which channel layers of ehnancement transistors or depletion type transistors which are adjacent in a horizontal direction.or.a vertical direction are continued.

Claim 8

A semiconductor memory comprising a plurality of row lines, a plurality of column lines being wired at light angles to said row lines, a plurality of memory cells positioned at crossing points of said row lines and said column lines, a first means coupled to said row lines for selecting one row line to read data out of a memory cell coupled to that row line in response to an address, a second means coupled to said column lines to select one of column lines in response to the address, a high voltage terminal at which a high voltage is supplied in a data writing operation, a plurality of switching circuits inserted between said row lines and said high voltage terminal, and means for turning on only one of said switching circuit corresponding to a row line to which a memory cell designated by an address is coupled in a data write operation.

Claim 9

A semiconductor memory comprising a plurality of row lines, a plurality of column lines being wired at light angles to said row lines, a plurality of memory cells positioned at crossing points of said row lines and said column lines, a first means coupled to said row lines for selecting one row line to read data out of a memory cell coupled to that row line in response to an address, a second means coupled to said column lines to select one of column lines in response to the address, a high voltage terminal at which a high voltage is supplied in a data writing operation, a plurality of switching circuits inserted between said row lines and said high voltage terminal, and means for turning on only one of said switching circuit corresponding to a row line to which a memory cell designated by an address is coupled in a data write operation.

Claim 10

A semiconductor device comprising a plurality of memory cells coupled to a plurality of first lines and a plurality of second lines, a first decoder coupled to said first lines to select one of said first lines in response to a data read address in a data read operation, a second decoder coupled to said first lines to select only one first line among said plurality of first lines in response to a write address in a data write operation, and means for supplying a data writing voltage to the first line selected by said second decoder.

Claim 11

A semiconductor device comprising a plurality of memory cells coupled to a plurality of first lines and a plurality of second lines, a first decoder coupled to said first lines to select one of said first lines in response to a data read address in a data read operation, a second decoder coupled to said first lines to select only one first line among said plurality of first lines in response to a write address in a data write operation, and means for supplying a data writing voltage to the first line selected by said second decoder.