US4405995A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory drive
Assignee: Fujitsu Ltd
•
Filing: 1981-08-24
•
Granted: 1983-09-20
•
Expires: 2001-08-24
Abstract
Abstract An improved semiconductor memory device is provided, which has: (i) a first gate electrode in an electrically floating state, at least a part of which confronts a channel region of a semiconductor device and which is separated by an insulating layer from the channel region; (ii) a second gate electrode (i.e., a control electrode), at least a part of which confronts the first gate electrode and is separated by an insulating layer from the first gate electrode; and (iii) a third gate electrode (i.e., an erasing electrode), at least a part of which confronts the first gate electrode and is separated by an insulating layer from the first gate electrode. The insulating layer, separating at least a part of the erasing electrode from the first gate electrode, has a thickness (usually 50 to 300 A) sufficient to allow the passage of charges from the first gate electrode to the erasing electrode through a tunneling effect, thereby discharging the first gate electrode.
Inventors
- 👤 Kazunari Shirai
- 👤 Izumi Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:24
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
191 words
An improved semiconductor memory device formed on a substrate having a channel region, comprising: an insulating layer formed on the channel region; a first gate electrode, formed on the insulating layer, in an electrically floating state, at least a part of which being positioned over the channel region of the semiconductor device and being separated by the insulating layer from the channel region; a second gate electrode, formed over the first gate electrode, comprising a control electrode, at least a part of which facing the first gate electrode and being separated by the insulating layer from the first gate electrode; and a third gate electrode, formed over the first gate electrode, the second gate electrode and the channel region, comprising an erasing electrode, at least a part of which facing the first gate electrode and being separated by the insulating layer from the first gate electrode; said insulating layer separating at least a part of the erasing electrode from the first gate electrode having a thickness sufficient to allow passage of charges from the first gate electrode to the erasing electrode through a tunneling effect, thereby discharging the first gate electrode.
Claim 2
Dependent Claim
191 words
An improved semiconductor memory device formed on a substrate having a channel region, comprising: an insulating layer formed on the channel region; a first gate electrode, formed on the insulating layer, in an electrically floating state, at least a part of which being positioned over the channel region of the semiconductor device and being separated by the insulating layer from the channel region; a second gate electrode, formed over the first gate electrode, comprising a control electrode, at least a part of which facing the first gate electrode and being separated by the insulating layer from the first gate electrode; and a third gate electrode, formed over the first gate electrode, the second gate electrode and the channel region, comprising an erasing electrode, at least a part of which facing the first gate electrode and being separated by the insulating layer from the first gate electrode; said insulating layer separating at least a part of the erasing electrode from the first gate electrode having a thickness sufficient to allow passage of charges from the first gate electrode to the erasing electrode through a tunneling effect, thereby discharging the first gate electrode.
Claim 3
Dependent Claim
46 words
A semiconductor memory device according to claim 1, wherein said first gate electrode has a side wall, and wherein at least a part of the side wall of the first gate electrode is separated from the erasing electrode by said insulating layer having a first thickness.
Claim 4
Dependent Claim
37 words
A semiconductor memory device according to claim 1 or 2, wherein said first thickness of said insulating layer, separating at least a part of the erasing electrode from the first gate electrode, is 50 to 300 angstroms.
Claim 5
Dependent Claim
37 words
A semiconductor memory device according to claim 1 or 2, wherein said first thickness of said insulating layer, separating at least a part of the erasing electrode from the first gate electrode, is 100 to 200 angstroms.
Claim 6
Dependent Claim
39 words
A semiconductor memory device according to claim 1 or 2, wherein said insulating layer, separating at least a part of the erasing electrode from the first gate electrode, being formed by oxidizing a surface of the first gate electrode.
Claim 7
Dependent Claim
65 words
A semiconductor memory device according to claim 1, wherein one or more pairs of first gate electrodes and one or more pairs of control electrodes are disposed so that the two first gate electrodes in each pair are symmetric to each other, relative to the erasing electrode, and the two control electrodes in each pair are symmetric to each other, relative to the erasing electrode.
Claim 8
Dependent Claim
161 words
A semiconductor memory device, comprising: a substrate; a channel cut region of a first conductivity formed in said substrate; a power line region of a second conductivity formed on said channel cut region; a first insulating layer formed on said power line region and said substrate; a floating gate electrode formed on said first insulating layer; a second insulating layer formed on a first portion of said floating gate electrode, so that a second portion of said floating gate electrode is exposed; a control electrode formed on said second insulating layer; a third insulating layer formed on said control electrode and the second portion of said floating gate electrode; and an erasing electrode formed on said third insulating layer and said first insulating layer and facing both said floating gate electrode said control electrode, and said third insulating layer between said erasing electrode and said floating gate electrode having a first thickness sufficient to cause an electron tunneling effect to occur.
Claim 9
Dependent Claim
161 words
A semiconductor memory device, comprising: a substrate; a channel cut region of a first conductivity formed in said substrate; a power line region of a second conductivity formed on said channel cut region; a first insulating layer formed on said power line region and said substrate; a floating gate electrode formed on said first insulating layer; a second insulating layer formed on a first portion of said floating gate electrode, so that a second portion of said floating gate electrode is exposed; a control electrode formed on said second insulating layer; a third insulating layer formed on said control electrode and the second portion of said floating gate electrode; and an erasing electrode formed on said third insulating layer and said first insulating layer and facing both said floating gate electrode said control electrode, and said third insulating layer between said erasing electrode and said floating gate electrode having a first thickness sufficient to cause an electron tunneling effect to occur.
Claim 10
Dependent Claim
28 words
A semiconductor memeory device according to claim 7, wherein said first thickness being greater than or equal to 50 angstroms and less than or equal to 300 angstroms.
Claim 11
Dependent Claim
28 words
A semiconductor memory device according to claim 7, wherein said first thickness being greater than or equal to 100 angstroms and less than or equal to 300 angstroms.
Claim 12
Dependent Claim
52 words
A semiconductor memory device according to claim 7, 8 or 9, further comprising: a bit line region of the second conductivity formed in said substrate; a fourth insulating layer formed on said erasing electrode; and a bit line formed on said fourth insulating layer and in contact with said bit line region.
References Cited (Backward Citations)
US3825946A
Cited
US4161039A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-19 | 1987-03-21 | 1987-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-19 | 1991-03-21 | 1991-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-19 | 1995-03-21 | 1995-09-20 | $7700.00 | Window Closed / Lapsed |