Small contactless RAM cell

Claim 2

An integrated MOS transistor structure comprising: a) contiguous source, drain and channel regions in a substrate; b) a gate electrode above said substrate between said source and drain regions and insulated therefrom; c) a first doped polysilicon conductor in electrical contact with said source region; d) a second doped polysilicon conductor in electrical contact with said drain region; said gate electrode, said first and said second polysilicon conductors comprising a single, etched layer of polysilicon, said single etched layer forming all electrical connections between said transistor and another transistor in a common cell with said transistor, said single layer of polysilicon also forming source, drain, and gate conductors of said another transistor; and e) contact windows for electrically connecting a metal layer to said single etched layer of polysilicon, each of said contact windows is formed outside of said cell area of said transistors.

Claim 3

A static RAM cell consisting essentially of: a semiconductor body having a major surface; first, second, third, fourth, fifth, and sixth MOS transistors formed in discrete regions of said semiconductor body, each transistor comprising source, channel, and drain regions, contiguous in the order stated, formed in said semiconductor body and abutting said major surface, each of said source and drain regions being doped to one of first and second conductivity types, said channel region being doped to the other of the first and second conductivity types, a doped polysilicon gate electrode having at least a portion overlying and insulated from said channel region, a doped polysilicon source electrode in direct electrical contact with said source region along said major surface and terminating on said major surface at a first location laterally spaced from said gate electrode, a doped polysilicon drain electrode in direct electrical contact with said drain region along said major surface and terminating on said major surface at a second location laterally spaced from said gate electrode, and a layer of refractory metal silicide overlying and substantially coextensive with said source, drain, and gate electrodes; a first shared node of doped polysilicon which is an extension of an electrically connects the gate electrodes of said first and fifth transistors, the source electrodes of said third and fourth transistors, and the drain electrode of said second transistor; a second shared node of doped polysilicon which is an extension of and electrically connects the gate electrodes of said second and fourth transistors, the source electrodes of said fifth and sixth transistors, and the drain of said first transistor; a word line interconnection of doped polysilicon which is an extension of and electrically connects the gate electrodes of said third and sixth transistors; a power supply interconnection of doped polysilicon which is an extension of and electrically connects individually to the drain electrodes of said fourth and fifth transistors; a reference voltage interconnection of doped polysilicon which is an extension of and electrically connects individually to the source electrodes of said first and second transistors; first and second bit line interconnections which are extension of and which electrically connect to the drain electrodes of said third and sixth transistors respectively; and a layer of refractory metal silicide overlying and substantially coextensive with said shared nodes and interconnections.

Claim 4

A static RAM cell consisting essentially of: a semiconductor body having a major surface; first, second, third, fourth, fifth, and sixth MOS transistors formed in discrete regions of said semiconductor body, each transistor comprising source, channel, and drain regions, contiguous in the order stated, formed in said semiconductor body and abutting said major surface, each of said source and drain regions being doped to one of first and second conductivity types, said channel region being doped to the other of the first and second conductivity types, a doped polysilicon gate electrode having at least a portion overlying and insulated from said channel region, a doped polysilicon source electrode in direct electrical contact with said source region along said major surface and terminating on said major surface at a first location laterally spaced from said gate electrode, a doped polysilicon drain electrode in direct electrical contact with said drain region along said major surface and terminating on said major surface at a second location laterally spaced from said gate electrode, and a layer of refractory metal silicide overlying and substantially coextensive with said source, drain, and gate electrodes; a first shared node of doped polysilicon which is an extension of an electrically connects the gate electrodes of said first and fifth transistors, the source electrodes of said third and fourth transistors, and the drain electrode of said second transistor; a second shared node of doped polysilicon which is an extension of and electrically connects the gate electrodes of said second and fourth transistors, the source electrodes of said fifth and sixth transistors, and the drain of said first transistor; a word line interconnection of doped polysilicon which is an extension of and electrically connects the gate electrodes of said third and sixth transistors; a power supply interconnection of doped polysilicon which is an extension of and electrically connects individually to the drain electrodes of said fourth and fifth transistors; a reference voltage interconnection of doped polysilicon which is an extension of and electrically connects individually to the source electrodes of said first and second transistors; first and second bit line interconnections which are extension of and which electrically connect to the drain electrodes of said third and sixth transistors respectively; and a layer of refractory metal silicide overlying and substantially coextensive with said shared nodes and interconnections.

Claim 5

A static RAM cell as defined in claim 2 where at least one of said polysilicon electrodes extends to a region outside the discrete region of its associated transistor.