EP0097595A2
Expired / Lapsed
EP
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Static RAM cell
Assignee: Fairchild Semiconductor Corp
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Filing: 1983-06-21
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Granted: —
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Expires: 2003-06-21
Abstract
Abstract A static RAM cell (11) is constructed utilizing low resistivity positive and negative power supply leads (13, 14), thus eliminating the problem of instability of the data stored within the cell. The negative power supply lead is formed of a first layer of low resistivity polycrystalline silicon/tantalum silicide, and the positive power supply lead is formed of a second layer of polycrystalline silicon. By the use of a low resistivity negative power supply lead, the voltage drop on the negative power supply lead is substantially reduced as compared with prior art devices, thereby providing during the read operation substantially equal voltages to the gates of the two bistable transistors of each cell, thus eliminating the problem of instability during reading. Depletion load devices (11, 12) are formed utilizing the layer of polycrystalline silicon as the source, drain and channel and the layer of polycrystalline silicon/tantalum I silioide as the gate. In this manner, silicon area is not I required to form the depletion load devices, thus minimizing cell size.
Inventors
- 👤 Peter Chen-Yu Chen
- 👤 Alex Au
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 20:58
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H10B; H10B10/00; H10B10/12; H10B10/125; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/84
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
246 words
A semiconductor memory cell capable of storing a single binary digit (bit) comprising : - a first and a second voltage supply lead (13, 14) ; - a word line (23), a bit line (19) and a bit line (20; - a first and a second transistor (17, 18) each having a drain and each having a gate connected to said word line (23), said source of said first transistor (17) being connected to said bit line (19), and said source of said second transistor (18) being connected to said bit line (20) ; - a third and a fourth transistor (15, 16) each having a gate and a drain and each having a source connected to said second voltage supply lead (14), said gate of said third transistor (15) being connected to said drain of said first transistor (17) and to said drain of said fourth transistor (16), said gate of said fourth transistor (16) being connected to said drain of said second transistor (18) and to said drain of said third transistor (15) ; and - a first and a second load device (11, 12), said first load device (11) connected between said first voltage supply lead (13) and said gate of said third transistor (15) and said second load device (12) connected between said first voltage supply lead (13) and said gate of sai3 fourth transistor (16) ; - characterized in that said second voltage supply lead (14) is a low resistivity lead.
Claim 2
Dependent Claim
246 words
A semiconductor memory cell capable of storing a single binary digit (bit) comprising : - a first and a second voltage supply lead (13, 14) ; - a word line (23), a bit line (19) and a bit line (20; - a first and a second transistor (17, 18) each having a drain and each having a gate connected to said word line (23), said source of said first transistor (17) being connected to said bit line (19), and said source of said second transistor (18) being connected to said bit line (20) ; - a third and a fourth transistor (15, 16) each having a gate and a drain and each having a source connected to said second voltage supply lead (14), said gate of said third transistor (15) being connected to said drain of said first transistor (17) and to said drain of said fourth transistor (16), said gate of said fourth transistor (16) being connected to said drain of said second transistor (18) and to said drain of said third transistor (15) ; and - a first and a second load device (11, 12), said first load device (11) connected between said first voltage supply lead (13) and said gate of said third transistor (15) and said second load device (12) connected between said first voltage supply lead (13) and said gate of sai3 fourth transistor (16) ; - characterized in that said second voltage supply lead (14) is a low resistivity lead.
Claim 3
Dependent Claim
17 words
Structure as in Claim 1 characterized in that said first voltage supply lead (13) comprises polycrystalline silicon.
Claim 4
Dependent Claim
19 words
Structure as in Clain 1 or 2 characterized in that said second voltage supply lead (14) comprises polycrystalline silicon.
Claim 5
Dependent Claim
19 words
Structure as in Clain 1 or 2 characterized in that said second voltage supply lead (14) comprises polycrystalline silicon.
Claim 6
Dependent Claim
47 words
Structure as in Claim 1 characterized in that said second voltage supply lead (14) comprises a first layer of polycrystalline silicon and said first voltage supply lead (13) comprises a second layer of polycrystalline silicon located above and spaced apart from said first layer of polycrystalline silicon.
Claim 7
Dependent Claim
19 words
Structure as in Claim 4 characterized in that said first layer of polycrystalline silicon also comprises a metal silicide.
Claim 8
Dependent Claim
25 words
Structure as in Claim 5 characterized in that said metal silicide is selected from the group consisting of titanium silicide, tungsten silicide and molybdenum silicide.
Claim 9
Dependent Claim
23 words
Structure as in any one of Claims 1 to 6 characterized in that said first and second load devices (11, 12) comprise resistors.
Claim 10
Dependent Claim
30 words
Structure as in any one of Claims 1 to 6 characterized in that said first and second load devices (11, 12) comprise a first and a second depletion load transistor.
Claim 11
Dependent Claim
83 words
Structure as in Claim 8 characterized in that said first depletion load transistor (11) comprises a transistor having its gate and its source connected in common to said gate of said third transistor (15) and its drain connected to said first voltage supply lead (13), and said second depletion load transistor (12) comprises a transistor having its gate and its source connected in common to said gate of said fourth transistor (16) and its drain connected to said first voltage supply lead (13).
Claim 12
Dependent Claim
47 words
Structure as in Claim 9 characterized in that each said load transistor (11, 12) comprises a first layer of polycrystalline silicon serving as the source, drain and channel of said load transistor, and a gate formed of polycrystalline silicon located above and electrically insulated from said channel.
References Cited (Backward Citations)
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