CMOS device with both p+ and n+ gates

Claim 2

An integrated circuit device comprising: (a) a first transistor having a first gate, said first gate being made of semiconductor material of a first conductivity type and covered with a conductive first thin film layer; (b) a second transistor having a second gate, said second gate being made of semiconductor material of a second conductivity type which is opposite to said first conductivity type, said second transistor gate having a conductive second thin film layer spacially isolated from said first thin film layer; (c) an interconnect layer distinct from said first and second thin film layers, said interconnect layer comprising titanium nitride, said interconnect layer ohmically connecting the conductive first thin film layer of said first gate with the conductive second thin film layer of said second gate.

Claim 3

The device of claim 1 wherein said interconnect layer comprising titanium nitride provides the only ohmic connection between the first and second thin film layers.

Claim 4

The device of claim 1 wherein connection between said interconnect layer and the first and second thin film layers is made without forming contact holes through any insulative layers.

Claim 5

The integrated circuit device of claim 1, wherein said first and said second transistors form a CMOS inverter.

Claim 6

The integrated circuit device of claim 1, wherein said first transistor is a P-channel insulated gate field effect transistor and said second transistor is an N-channel insulated gate field effect transistor.

Claim 7

The integrated circuit device of claim 1, wherein said first conductivity type is P-type and said second conductivity type is N-type.

Claim 8

The integrated circuit device of claim 1, wherein the conductive first thin film layer is a silicide.

Claim 9

The integrated circuit device of claim 7, wherein said silicide is titanium disilicide.

Claim 10

The integrated circuit device of claim 1, wherein said gates are each formed as a layered structure.

Claim 11

The integrated circuit device of claim 9, wherein each said layered structure comprises at least one layer consisting essentially of polycrystalline silicon.

Claim 12

The integrated circuit of claim 10, wherein at least one layer of said gates includes a substantial fraction of a metal silicide.

Claim 13

The integrated circuit device of claim 10, wherein at least one layer of each said gate includes a substantial fraction of a refractory metal.

Claim 14

The integrated circuit device of claim 1, wherein the majority of said first and said second transistors each comprise an effective channel length less than one micron.

Claim 15

The integrated circuit device of claim 6, wherein said interconnect layer forms a diffusion barrier to P-type and N-type dopants in said first and said second gates.

Claim 16

An integrated circuit device comprising: (a) a first transistor having a first gate, said first gate being made of semiconductor material of a first conductivity type and covered with a conductive first thin film layer; (b) a second transistor having a second gate, said second gate being made of semiconductor material of a second conductivity type which is opposite to said first conductivity type, said second transistor gate having a conductive second thin film layer said second gate spacially isolated from said first gate; (c) an interconnect layer distinct from said first and second thin film layers, said interconnect layer comprising titantium nitride, said interconnect layer ohmically connecting said first and second gates.

Claim 17

An integrated circuit device comprising: (a) a first transistor having a first gate, said first gate being made of semiconductor material of a first conductivity type and covered with a conductive first thin film layer; (b) a second transistor having a second gate, said second gate being made of semiconductor material of a second conductivity type which is opposite to said first conductivity type, said second transistor gate having a conductive second thin film layer said second gate spacially isolated from said first gate; (c) an interconnect layer distinct from said first and second thin film layers, said interconnect layer comprising titantium nitride, said interconnect layer ohmically connecting said first and second gates.

Claim 18

The device of claim 15 wherein connection between said interconnect layer and said first and second gates is made without forming contact holes through any insulative layers.

Claim 19

The device of claim 15 wherein said interconnect layer comprising titanium nitride provides the only ohmic connection between said first and second gates.

Claim 20

The device of claim 16 wherein said interconnect layer provides the only ohmic connection between said first and second gates.

Claim 21

The device of claim 18 wherein said first and second transistors form a CMOS inverter.

Claim 22

The integrated circuit device of claim 15 wherein said first and said second transistor form a CMOS inverter.

Claim 23

The integrated circuit device of claim 15 wherein said first transistor is a P-channel insulated gate field effect transistor and said second transistor is an N-channel insulated gate field effect transistor.

Claim 24

The integrated circuit device of claim 15 wherein said first conductivity type is P-type and said second conductivity type is N-type.

Claim 25

The integrated circuit device of claim 15 wherein the conductive first thin film layer is a silicide.

Claim 26

The integrated circuit device of claim 15 wherein each gate comprises at least one conductive layer consisting essentially of silicon.

Claim 27

The integrated circuit device of claim 22 wherein said interconnect layer forms a diffusion barrier to P-type and N-type dopants in said first and said second gates.

Claim 28

The integrated circuit device of claim 23 wherein said interconnect layer forms a diffusion barrier to P-type and N-type dopants in said first and said second gates.

Claim 29

The device of claim 15 wherein said semiconductor material predominantly comprises silicon.

Claim 30

The device of claim 15 wherein said gates comprise polysilicon and said thin film layers comprise titanium silicide.

Claim 31

An integrated circuit device, comprising: an isolation structure defining first and second moat regions; a first transistor formed in said first moat region and having a gate, said gate of said first transistor comprising a semiconductor material of a first conductivity type and a layer of a refractory metal silicide overlying said semiconductor material; a second transistor formed in said second moat region and having a gate, said gate of said second transistor comprising a semiconductor material of a second conductivity type and a layer of a refractory metal silicide overlying said semiconductor material; an interconnect comprising titanium nitride, said interconnect extending over said isolation structure and connecting the gates of said first and said second transistors.

Claim 32

An integrated circuit device, comprising: an isolation structure defining first and second moat regions; a first transistor formed in said first moat region and having a gate, said gate of said first transistor comprising a semiconductor material of a first conductivity type and a layer of a refractory metal silicide overlying said semiconductor material; a second transistor formed in said second moat region and having a gate, said gate of said second transistor comprising a semiconductor material of a second conductivity type and a layer of a refractory metal silicide overlying said semiconductor material; an interconnect comprising titanium nitride, said interconnect extending over said isolation structure and connecting the gates of said first and said second transistors.

Claim 33

The device of claim 29, wherein said gate of said second transistor has an extended portion disposed upon said isolation structure.

Claim 34

The device of claim 30, wherein said interconnect is in contact with said extended portion of said gate of said second transistor.

Claim 35

The device of claim 31, wherein said gate of said first transistor has an extended portion disposed upon said isolation structure.

Claim 36

The device of claim 32, wherein said interconnect is in contact with said extended portion of said gate of said first transistor.

Claim 37

The device of claim 29, wherein said first transistor has a channel region of said second conductivity type and source and drain regions of said first conductivity type.

Claim 38

The device of claim 34, wherein said second transistor has a channel region of said first conductivity type and source and drain regions of said second conductivity type.

Claim 39

The device of claim 29, wherein said second transistor has a channel region of said first conductivity type and source and drain regions of said second conductivity type.

Claim 40

The device of claim 29, wherein said interconnect is in contact with said layer of refractory metal silicide of each of said gates.

Claim 41

An integrated circuit device, comprising: an isolation structure defining first and second moat regions; a first transistor formed in said first moat region and having a gate, said gate of said first transistor comprising a semiconductor material of a first conductivity type and a layer of a refractory metal silicide overlying said semiconductor material; a second transistor formed in said second moat region and having a gate, said gate of said second transistor comprising a semiconductor material of a second conductivity type and a layer of a refractory metal silicide overlying said semiconductor material; an interconnect extending over said isolation structure and connecting the gates of said first and said second transistors, said interconnect comprising a conductive refractory metal compound which substantially prevents dopant from said gate of said first transistor from diffusing to said gate of said second transistor.

Claim 42

An integrated circuit device, comprising: an isolation structure defining first and second moat regions; a first transistor formed in said first moat region and having a gate, said gate of said first transistor comprising a semiconductor material of a first conductivity type and a layer of a refractory metal silicide overlying said semiconductor material; a second transistor formed in said second moat region and having a gate, said gate of said second transistor comprising a semiconductor material of a second conductivity type and a layer of a refractory metal silicide overlying said semiconductor material; an interconnect extending over said isolation structure and connecting the gates of said first and said second transistors, said interconnect comprising a conductive refractory metal compound which substantially prevents dopant from said gate of said first transistor from diffusing to said gate of said second transistor.

Claim 43

The device of claim 38, wherein said interconnect is in contact with said layer of refractory metal silicide of each of said gates.

Claim 44

The device of claim 38, wherein said interconnect layer comprises a refractory metal nitride.

Claim 45

The device of claim 38, wherein said interconnect layer comprises titanium nitride.