Patent US4947232A successfully refreshed from Google Patents.
US4947232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage MOS transistor
Assignee: Sharp Corp
•
Filing: 1988-11-28
•
Granted: 1990-08-07
•
Expires: 2008-11-28
Abstract
Abstract A metal oxide semiconductor device is featured by the provision of a covering element for covering a channel region of the semiconductor device there being interposed therebetween an insulating layer. The covering element is connected to at least one electrode selected from the drain electrode, the source electrode and the gate electrode. Therefore, the electrical level of the covering element is fixed.
Inventors
- 👤 Tsutomu Ashida
- 👤 Kiyotoshi Nakagawa
- 👤 Katsumasa Fujii
- 👤 Yasuo Torimaru
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:19
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/111; H10D64/115; H10D30/00; H10D30/60; H10D30/601; H10D30/603
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
409 words
A metal oxide semiconductor device of a high voltage type which prevents field concentration near the edge of a gate electrode, eliminates a reverse field plate effect and provides for stable driving operation of said device comprising in cross section: a semiconductor substrate comprising an upper surface having a conductivity of a first type; a source region having a conductivity of a second type opposite to that of said semiconductor substrate formed in the surface of said substrate; a drain region having a conductivity of said second type opposite to that of said semiconductor substrate formed in the surface of said substrate apart from said source region; a gate channel region having the same conductivity type as said semiconductor substrate connected to said source region within said substrate; a field dope region positioned adjacent and outside said gate channel region at the surface of said substrate having a conductivity the same as said first type; a high resistance region of said second type conductivity disposed substantially at the surface of said substrate between said source and drain regions connected to said drain region and separated by a portion of said substrate from said gate channel region; a continuous insulating layer overlying a portion of said source region, a portion of said gate channel region, said high resistance region and a portion of said drain region; a drain electrode connected to said drain region having a field plate layer portion extending radially inwardly from said drain electrode; a source electrode connected to said source region, said gate channel region and said field dope region, having a field plate layer portion extending radially inwardly from said source electrode; a gate electrode formed above said gate channel region within said continuous insulating layer having a portion of said continuous insulating layer interpositioned between said gate electrode and said substrate; and a high resistance covering layer substantially overlying said high resistance region so as to provide said high resistance region with a constant electric field and to eliminate influence by external charges, said continuous insulating layer being interposed between said high resistance covering layer and said high resistance region, said high resistance covering layer having first and second terminal end portions of low resistance connecting said high resistance covering layer by said first end to said drain electrode and by said second end to said source electrode through said respective radially extending field plate layer portion extension or directly to said gate electrode.
Claim 2
Dependent Claim
409 words
A metal oxide semiconductor device of a high voltage type which prevents field concentration near the edge of a gate electrode, eliminates a reverse field plate effect and provides for stable driving operation of said device comprising in cross section: a semiconductor substrate comprising an upper surface having a conductivity of a first type; a source region having a conductivity of a second type opposite to that of said semiconductor substrate formed in the surface of said substrate; a drain region having a conductivity of said second type opposite to that of said semiconductor substrate formed in the surface of said substrate apart from said source region; a gate channel region having the same conductivity type as said semiconductor substrate connected to said source region within said substrate; a field dope region positioned adjacent and outside said gate channel region at the surface of said substrate having a conductivity the same as said first type; a high resistance region of said second type conductivity disposed substantially at the surface of said substrate between said source and drain regions connected to said drain region and separated by a portion of said substrate from said gate channel region; a continuous insulating layer overlying a portion of said source region, a portion of said gate channel region, said high resistance region and a portion of said drain region; a drain electrode connected to said drain region having a field plate layer portion extending radially inwardly from said drain electrode; a source electrode connected to said source region, said gate channel region and said field dope region, having a field plate layer portion extending radially inwardly from said source electrode; a gate electrode formed above said gate channel region within said continuous insulating layer having a portion of said continuous insulating layer interpositioned between said gate electrode and said substrate; and a high resistance covering layer substantially overlying said high resistance region so as to provide said high resistance region with a constant electric field and to eliminate influence by external charges, said continuous insulating layer being interposed between said high resistance covering layer and said high resistance region, said high resistance covering layer having first and second terminal end portions of low resistance connecting said high resistance covering layer by said first end to said drain electrode and by said second end to said source electrode through said respective radially extending field plate layer portion extension or directly to said gate electrode.
Claim 3
Dependent Claim
71 words
The device of claim 1, wherein said high resistance covering layer comprises: a conductive segment disposed in a plane different from each of said field plate layer portions, respective high resistance materials at either end of said conductive segment, each of said high resistance materials having terminal end portions of low resistance connecting said conductive segment with said drain electrode and field plate layer extension portion of said source electrode, respectively.
Claim 4
Dependent Claim
28 words
The device of claim 2, further including at least one additional insulating layer, said insulating layer including at least one of said conductive segments and adjoining resistive materials.
References Cited (Backward Citations)
US964009A
Cited
SE300472B
Cited
US3967310A
Cited
DE2031082A1
Cited
US4157563A
Cited
CA963174A
Cited
US3890698A
Cited
US3841926A
Cited
US4009483A
Cited
UST964009I4
Cited
US4079504A
Cited
JPS5327374A
Cited
US4194214A
Cited
JPS5366181A
Cited
US4172260A
Cited
JPS5437584A
Cited
US4292729A
Cited
US4270137A
Cited
US4199774A
Cited
US4290077A
Cited
US4290078A
Cited
US4288803A
Cited
US4394674A
Cited
US4614959A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-06 | 1994-02-05 | 1994-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-06 | 1998-02-05 | 1998-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-06 | 2002-02-05 | 2002-08-07 | $7700.00 | Window Closed / Lapsed |