High voltage MOSFET with doped ring structure

Claim 2

A high voltage MOSFET in an integrated monolithic array on a substrate with a closed geometry configuration including a drain area having a relative center axis introduced in the substrate, a source area introduced in the substate relatively adjacent to the drain area, a channel area introduced in the substrate between the source area and the drain area, and a drift area introduced in the substrate between the channel area and the drain area, comprising: (a) field plate means relatively disposed in a first layer of relatively thick oxide over the drift area for application of a potential through the first layer of thick oxide to the drift area for controlling the breakdown voltage as between the source and drain area by contouring the field lines to bend away from the drain area; (b) gate electrode means relatively disposed in a second layer or relatively thin field oxide over the channel area for controlling the potential and for turning on and off the potential as between the source and drain areas and; (c) ring means implanted in the substrate to be relatively aligned with the spatial gaps occurring between said field plate means and said gate electrode means as doped areas for reducing resistance in the spatial gaps by providing a conductive path for carriers as between said gate electrode means and said field plate means.

Claim 3

The high voltage MOSFET of claim 1 wherein said ring means is a relative virtual drain able to enhance injection of electrons as carriers into the drift area when there is a potential as between the drain and source areas.

Claim 4

The high voltage MOSFET of claim 2 wherein said relative virtual drain is relatively heavily N+ doped.

Claim 5

The high voltage MOSFET of claim 2 wherein said relative virtual drain is relatively P type doped.

Claim 6

The high voltage MOSFET of claim 2 wherein said relative virtual drain is relatively neutral conductively implanted as to doping type.

Claim 7

The high voltage MOSFET of claim 2 wherein said relative virtual drain is relatively lightly N type doped.

Claim 8

The high voltage MOSFET of claim 6 wherein said relative virtual drain is relatively lightly N type doped that has been buried as a channel.

Claim 9

The high voltage MOSFET of claim 1 wherein said field plate means is conductivly neutral.

Claim 10

The high voltage MOSFET of claim 1 wherein said ring means are relatively offset but electrically connected.

Claim 11

The high voltage MOSFET of claim 1 wherein said ring means are relatively spatially multiple occurring with independent potentials applied to each thereof.

Claim 12

The high voltage MOSFET of claim 1 wherein said rings are tailored to provide a relatively uniform field drop in the lateral direction of the drain area to the source area.

Claim 13

The high voltage MOSFET of claim 1 wherein said rings are relatively lightly N-type doped.

Claim 14

The high voltage MOSFET of claim 1 wherein said rings are relatively P-type doped.

Claim 15

The high voltage MOSFET of claim 1 wherein said rings are relatively P+type doped.

Claim 16

The high voltage MOSFET of claim 1 wherein said field plate means relatively spatially occur in multiples.

Claim 17

The high voltage MOSFET of claim 1 wherein said field plate means is a polysilicon layer.

Claim 18

The high voltage MOSFET of claim 1 wherein said gate electrode means is a polysilicon layer.

Claim 19

The high voltage MOSFET of claim 1 wherein said field plate means and the drain area are electrically uncoupled.

Claim 20

A HV metal oxide semiconductor FET structure for a driver array having a monolithic integrated closed geometry configuration on a substrate, comprising; (a) first means having a relative center axis implanted in the substrate for function as a drain region, second means implanted in the substrate relatively adjacent to said first means for function as a source region, third means implanted in the substrate relatively interdisposed between said second and first means for function as a channel region, and fourth means implanted in the substrate relatively interdisposed between said third and first means for function as a drift region; (b) field means relatively embedded in a first layer of relatively thick oxide above fourth means for applying a potential to said fourth means for controlling the breakdown voltage as between said second and first means by contouring the field lines to bend away from the drain area, and (c) gate means relatively embedded in a second layer of relatively thin oxide over said third means for controlling the potential and for turning on and off the current between said first and second means; and; (d) ring means relatively disposed in the substrate to be aligned with the gaps occurring between said field means and said gate means as doped areas for reducing resistance in the spatial gaps by providing a conductive path for electrons as between said gate means and said field means.

Claim 21

A HV metal oxide semiconductor FET structure for a driver array having a monolithic integrated closed geometry configuration on a substrate, comprising; (a) first means having a relative center axis implanted in the substrate for function as a drain region, second means implanted in the substrate relatively adjacent to said first means for function as a source region, third means implanted in the substrate relatively interdisposed between said second and first means for function as a channel region, and fourth means implanted in the substrate relatively interdisposed between said third and first means for function as a drift region; (b) field means relatively embedded in a first layer of relatively thick oxide above fourth means for applying a potential to said fourth means for controlling the breakdown voltage as between said second and first means by contouring the field lines to bend away from the drain area, and (c) gate means relatively embedded in a second layer of relatively thin oxide over said third means for controlling the potential and for turning on and off the current between said first and second means; and; (d) ring means relatively disposed in the substrate to be aligned with the gaps occurring between said field means and said gate means as doped areas for reducing resistance in the spatial gaps by providing a conductive path for electrons as between said gate means and said field means.

Claim 22

The HV metal oxide semiconductor FET structure of claim 15 wherein said ring means is a virtual drain able to enhance injection of electrons into said fourth means when there is a relative potential between siad first and second means.

Claim 23

The HV metal oxide semiconductor FET structure of claim 15 wherein said virtual drain is relatively heavily N+ type doped.

Claim 24

The HV metal oxide semiconductor FET structure of claim 19 wherein said virtual drain is relatively P type doped.

Claim 25

The HV metal oxide semiconductor FET structure of claim 19 wherein said virtual drain is relatively neutrally implanted as to doping type.

Claim 26

The HV metal oxide semiconductor FET structure of claim 19 wherein said virtual drain is relatively lightly N type doped.

Claim 27

The HV metal oxide semiconductor FET structure of claim 20 is relatively lightly N type doped that has been buried as a channel.