Single-electrode charge-coupled random access memory cell with impurity implanted gate region

Claim 1

A charge coupled random access memory array comprising: a semiconductor body having embodied therein an impurity of a first conductivity type, a plurality of charge coupled memory cells arranged in columns and rows on said body, bit lines extending in the column direction, each bit line in operative relation to a column of said cells, word lines extending in the row direction, each word line in operative relation to a row of said cells, each of said cells comprised of a first region in said semiconductor body formed of an impurity of a second opposite conductivity type, said first region of said cell in operative electrical connection with one of said bit lines, a second region in said body in adjacent lateral relationship to said first region in the row direction and having embodied therein an impurity of a first conductivity type in a concentration greater than the concentration of the impurity in said semiconductor body, a third region in said body in adjacent lateral relationship to said second region, and spaced from said first region by said second region and having embodied therein an impurity of a first conductivity type in a concentration less than the concentration in said second region, said third region spaced from the first region of the adjacent memory cell, the threshold voltage of said second region being higher in absolute magnitude than the threshold voltage of said third region, the threshold voltages of said second and third regions being determined at least in part by the relative impurity concentrations in said second and third regions, a surface layer of dielectric material overlying at least said second region and said third region, a single conductive electrode on said surface layer of dielectric material and extending over said second and third regions in superimposed relation and in operative electrical connection with one of said word lines, said electrode having a first portion over said second region of said body and a second portion over said third region of said body, a means of applying at least two voltage levels to said conductive electrode to control the storage of charges in, and flow of charges to, said third region, the first of said voltage levels applied to said conductive electrode is of an absolute magnitude less than said first predetermined threshold voltage of said second region, but equal to or greater than said second threshold voltage of said third region, thereby inverting only said third region for charge storage capability, the second of said voltage levels of an absolute magnitude equal to or greater than said first predetermined threshold voltage of said second region thereby inverting both of said second and third regions for charge flow capability.