Patent US4897704A successfully refreshed from Google Patents.
US4897704A
Expired / Lapsed
US
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Lateral bipolar transistor with polycrystalline lead regions
Assignee: Mitsubishi Electric Corp
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Filing: 1988-02-24
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Granted: 1990-01-30
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Expires: 2008-02-24
Abstract
Abstract A semiconductor device of a type of a sidewall base contact structure transistor, comprising a semiconductor substrate of first conductive type; a transistor structure including a first collector region of a second conductive type, a second collector region of the second conductive type the impurity density of which region is lower than that of the first collector region, a base region of the first conductive type, and an emitter region of the second conductive type, each of the four regions being composed of a single crystalline semiconductor layer, formed one after another in the mentioned order on the main surface of the semiconductor substrate; an insulating layer provided on the main surface of the semiconductor substrate, surrounding the first and second collector regions, the base region, and the emitter region; a collector lead region embedded in the insulating layer, one end of the region being in contact with the side wall of the first collector region, the other end of the region being exposed from a part of the surface of the insulating layer; a base lead region embedded in the insulating layer, one end of the region being in contact with the side wall of the base region, the other end of the region being exposed from a part of the surface of the insulating layer other than the part where the other end of the collector lead region is exposed. This application is a continuation of application Ser. No. 861,755, filed on May 9, 1986, now abandoned, which is a continuation of application Ser. No. 566,682, filed on Dec. 29, 1983, now abandoned.
Inventors
- 👤 Hiromi Sakurai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:47
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/34; H10D48/345; H10D10/00; H10D10/40; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10W20/00; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
418 words
A semiconductor device comprising: a silicon substrate of a first electrically conductive type; an embedded collector layer of a second electrically conductive type opposite to said first electrically conductive type formed in said substrate, said embedded collector layer including first and second portions having predetermined surface areas, wherein said first portion of said embedded collector layer forms a PN junction with said substrate; a transistor structure disposed above said substrate including, a first collector region of said second electrically conductive type having a surface area substantially the same as said predetermined surface area of said first portion formed on said second portion of said embedded collector layer, a second collector region of said second electrically conductive type having a surface area substantially the same as said predetermined surface area of said first portion formed on said first collector region having an impurity density lower than that of said first collector region, a base region of said first electrically conductive type having a surface area substantially the same as said predetermined surface area of said first portion formed on said second collector region, and a first emitter region of said second electrically conductive type having a surface area substantially the same as said predetermined surface area of said first portion formed on said base region, wherein said first collector region, said second collector region, said base region, and said emitter region comprise a single crystalline silicon layer; an insulating layer provided on said substrate and surrounding said transistor structure; a first polycrystalline collector lead region formed in said insulating layer comprising said second electrically conductive type, said first collector lead region including first and second portions, wherein said first portion of said first collector lead region contacts said first collector region; a second polycrystalline collector lead region formed in said insulating layer comprising said second electrically conductive type, said second collector lead region including first and second portions, wherein said first portion of said second collector lead region contacts said second portion of said first collector lead region, and said second portion of said second collector lead region is exposed through said insulating layer so as to permit further electrical contacts therewith; and a polycrystalline base lead region of said first electrically conductive type, said base lead region including first and second portions, wherein said first portion of said base lead region contacts said base region, and said second portion of said base lead region is exposed through said insulating layer so as to permit further electrical contacts therewith.
Claim 2
Dependent Claim
418 words
A semiconductor device comprising: a silicon substrate of a first electrically conductive type; an embedded collector layer of a second electrically conductive type opposite to said first electrically conductive type formed in said substrate, said embedded collector layer including first and second portions having predetermined surface areas, wherein said first portion of said embedded collector layer forms a PN junction with said substrate; a transistor structure disposed above said substrate including, a first collector region of said second electrically conductive type having a surface area substantially the same as said predetermined surface area of said first portion formed on said second portion of said embedded collector layer, a second collector region of said second electrically conductive type having a surface area substantially the same as said predetermined surface area of said first portion formed on said first collector region having an impurity density lower than that of said first collector region, a base region of said first electrically conductive type having a surface area substantially the same as said predetermined surface area of said first portion formed on said second collector region, and a first emitter region of said second electrically conductive type having a surface area substantially the same as said predetermined surface area of said first portion formed on said base region, wherein said first collector region, said second collector region, said base region, and said emitter region comprise a single crystalline silicon layer; an insulating layer provided on said substrate and surrounding said transistor structure; a first polycrystalline collector lead region formed in said insulating layer comprising said second electrically conductive type, said first collector lead region including first and second portions, wherein said first portion of said first collector lead region contacts said first collector region; a second polycrystalline collector lead region formed in said insulating layer comprising said second electrically conductive type, said second collector lead region including first and second portions, wherein said first portion of said second collector lead region contacts said second portion of said first collector lead region, and said second portion of said second collector lead region is exposed through said insulating layer so as to permit further electrical contacts therewith; and a polycrystalline base lead region of said first electrically conductive type, said base lead region including first and second portions, wherein said first portion of said base lead region contacts said base region, and said second portion of said base lead region is exposed through said insulating layer so as to permit further electrical contacts therewith.
Claim 3
Dependent Claim
15 words
A semiconductor device as defined in claim 1, wherein the polycrystalline regions comprise polycrystalline silicon.
Claim 4
Dependent Claim
15 words
A semiconductor device as defined in claim 1, wherein the polycrystalline regions comprise polycrystalline silicide.
Claim 5
Dependent Claim
55 words
A semiconductor device as defined in claim 1, further comprising a second emitter region formed in said transistor structure between said base region and said first emitter region so as to form a bi-directional transistor structure, said second emitter region being of said second electrically conductive type, wherein said bi-directional transistor structure exhibits bi-directional properties.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-29 | 1993-07-31 | 1994-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-29 | 1997-07-31 | 1998-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-29 | 2001-07-31 | 2002-01-30 | $7700.00 | Window Closed / Lapsed |