Multipurpose switching circuits utilizing a novel semiconductor device

Claim 2

A switching circuit comprising; a. first and second current paths each formed with switching means and signal input means connected to said switching means, b. a current sink connected in common to both said first and second current paths, c. means for supplying a switching signal to both said switching means of the first and second current paths to cause them to switch alternately, d. a semiconductor device comprising a first semiconductor region of one type, a second semiconductor region of the other type adjacent said first region with a first semiconductor junction therebetween, a third semiconductor region of the same type as said first region adjacent said second region with a second semiconductor junction therebetween, said first region being provided therein with a potential barrier having energy higher than that of minority carriers injected from the second region to the first region at the position facing said first junction and apart from the same by a distance smaller than a diffusion distance of the minority carriers, and first, second and third terminals led from said first, second and third regions, respectively, said first and third terminals being connected to connection points between said switching means and said signal input means of both of said current paths, respectively, and e. signal output means connected to said second terminal of said semiconductor device for deriving therefrom a signal supplied through said signal input means in accordance with the switching operation of said switching means.

Claim 3

A switching circuit according to claim 1, wherein each of said switching means comprises a switching transistor with a collector-emitter path connected between said signal input means and said common current sink and a base connected to said switching signal supplying means.

Claim 4

A switching circuit according to claim 2, wherein each of said signal input means comprises an input transistor with a collector-emitter path connected in series to the collector-emitter path of said switching transistor and a base connected to be supplied with an input signal.

Claim 5

A switching circuit according to claim 3, wherein said signal output means comprises a load impedance connecting between said second terminal of the semiconductor device and an operating voltage source.

Claim 6

A switching circuit according to claim 4, wherein the bases of said input transistors are supplied with different input signals, respectively.

Claim 7

A switching circuit according to claim 4, wherein the bases of said input transistors are supplied with the same input signal differentially.

Claim 8

A switching circuit according to claim 4, wherein said switching and input transistors are said semiconductor devices.

Claim 9

A switching circuit according to claim 1, wherein said first and third regions of the semiconductor device have the impurity concentration in substantially the same order and said first region is provided therein a portion having the impurity concentration higher than other portions of the first region at the position apart from said first junction by a distance smaller than the diffusion distance of the minority carriers to make said potential barrier.

Claim 10

A switching circuit according to claim 1, wherein said first and third regions of the semiconductor device have the impurity concentration in substantially the same order and an additional semiconductor region of the same type as said second region is provided in said first region at the position apart from said first junction by a distance smaller than the diffusion distance of the minority carriers to make said potential barrier.

Claim 11

A switching circuit comprising: a. first and second current paths each formed by a series connection of a switching means and signal input means; b. a current sink connected in common to one end of both of said first and second current paths; c. means for differentially supplying a switching signal to both said switching means of the first and second current paths to cause them to switch alternately; d. a semiconductor device comprising a first semiconductor region of one conductivity type having a predetermined impurity concentration, a second semiconductor region of the opposite conductivity type having a predetermined impurity concentration interfaced with said first region and forming a first semiconductor PN junction with said first region, a third semiconductor region of the same conductivity type as said first region having a predetermined impurity concentration interfaced with said second region at a point spaced from said first junction and forming a second PN semiconductor junction with said second region, a fourth semiconductor region of the same conductivity type as said first region interfaced with said first region having a predetermined impurity concentration substantially higher than that of said first region and spaced from said first PN junction by a distance smaller than the diffusion length of minority carriers injected into said first region from said second region when said first PN junction is forwardly biased, said first and fourth regions forming a first low-high impurity concentration semiconductor junction at their interface, a fifth semiconductor region of the same conductivity type as said third region interfaced with said third region, having a predetermined impurity concentration substantially higher than that of said third region and spaced from said second PN junction by a distance smaller than the diffusion length of minority carriers injected into said third region from said second region when said second PN junction is forwardly biased, said third and fifth regions forming a second low-high impurity concentration semiconductor junction at their interface, the difference in impurity concentrations on opposite sides of each of said first and second low-high impurity concentration semiconductor junctions being selected to provide an energy barrier higher than the energy level of said injected minority carriers reaching said low-high impurity concentration junctions from said second region; e. first, second and third terminals led from said first, second and third regions, respectively, said first and third terminals being connected to first and second connection points between said switching means and said signal input means of each of said first and second current paths, respectively; and f. signal output means connected to said second terminal of said semiconductor device for deriving therefrom a signal supplied through said signal input means in accordance with the switching operation of said switching means.

Claim 12

A switching circuit comprising: a. first and second current paths each formed by a series connection of a switching means and signal input means; b. a current sink connected in common to one end of both of said first and second current paths; c. means for differentially supplying a switching signal to both said switching means of the first and second current paths to cause them to switch alternately; d. a semiconductor device comprising a first semiconductor region of one conductivity type having a predetermined impurity concentration, a second semiconductor region of the opposite conductivity type having a predetermined impurity concentration interfaced with said first region and forming a first semiconductor PN junction with said first region, a third semiconductor region of the same conductivity type as said first region having a predetermined impurity concentration interfaced with said second region at a point spaced from said first junction and forming a second PN semiconductor junction with said second region, a fourth semiconductor region of the same conductivity type as said first region interfaced with said first region having a predetermined impurity concentration substantially higher than that of said first region and spaced from said first PN junction by a distance smaller than the diffusion length of minority carriers injected into said first region from said second region when said first PN junction is forwardly biased, said first and fourth regions forming a first low-high impurity concentration semiconductor junction at their interface, a fifth semiconductor region of the same conductivity type as said third region interfaced with said third region, having a predetermined impurity concentration substantially higher than that of said third region and spaced from said second PN junction by a distance smaller than the diffusion length of minority carriers injected into said third region from said second region when said second PN junction is forwardly biased, said third and fifth regions forming a second low-high impurity concentration semiconductor junction at their interface, the difference in impurity concentrations on opposite sides of each of said first and second low-high impurity concentration semiconductor junctions being selected to provide an energy barrier higher than the energy level of said injected minority carriers reaching said low-high impurity concentration junctions from said second region; e. first, second and third terminals led from said first, second and third regions, respectively, said first and third terminals being connected to first and second connection points between said switching means and said signal input means of each of said first and second current paths, respectively; and f. signal output means connected to said second terminal of said semiconductor device for deriving therefrom a signal supplied through said signal input means in accordance with the switching operation of said switching means.

Claim 13

A switching circuit according to claim 10, in which said first and second potential barriers are spaced substantially the same distance from the first and second junctions, respectively.