Semiconductor device

Abstract

Abstract PURPOSE:To reduce the size of a transistor by means of a polycrystalline Si layer for drawing electrodes provided between a resistance element and a collector connection region when a bipolar transistor with a collector load resistance element is produced. CONSTITUTION:An n<+> type implanted region 2 is formed on a p type Si substrate 1 on the surface of which a p<+> type channel cut layer 3 is provided surrounding it. Then, an SiO2 film 4 is applied on the layer 3. After an n<-> type collector region 5 is formed on the region 2, a p<+> type active base region 6 is formed by diffusion at one end thereof while an n<+> type collector connection region 10 is formed by diffusion on the other end thereof. Thereafter, a p<+> type base drawing polycrystalline Si region 9 is positioned on the film 4 to be connected to the region 6 while an n<-> type polycrytalline resistance element 11a is provided on the region 10 in such a manner as to be positioned on the film 4 facing the region 9. Here, an n<+> type collector electrode for drawing a polycrystalline layer 7 is provided beforehand between the element 11a and the region 10. This can eliminate one terminal of the element 11a thereby reducing the size thereof.

Inventors

• 👤 Hiromi Sakurai
• 👤 Yoichi Akasaka

Bibliographic Details