Method for making germanium/gallium arsenide high mobility complementary logic transistors

Claim 1

A method of producing a germanium-gallium arsenide complementary logic transistor comprising the steps of: providing an undoped gallium arsenide substrate, growing a first layer of undoped GaAs epitaxial material on the substrate at a temperature less than 300° C., depositing a second layer of undoped amorphous germanium on the first layer at a temperature less than 320° C., heating the device to a temperature not to exceed 300° C. for crystalizing the germanium by solid phase epitaxy, implanting germanium ions and gallium ions into respective first regions of the first and second layers to create regions of high hole concentration, implanting germanium ions and arsenic ions respectively into second regions of the first and second layers to create regions of high electron concentration, rapid thermal annealing of the device, depositing an insulating layer onto appropriate portions of the device, and depositing metalization contacts over appropriate regions for providing control gates.

Claim 2

A method of producing a germanium-gallium arsenide complementary logic transistor comprising the steps of: providing an undoped gallium arsenide substrate, growing a first layer of undoped GaAs epitaxial material on the substrate at a temperature less than 300° C., depositing a second layer of undoped amorphous germanium on the first layer at a temperature less than 320° C., heating the device to a temperature not to exceed 300° C. for crystalizing the germanium by solid phase epitaxy, implanting germanium ions and gallium ions into respective first regions of the first and second layers to create regions of high hole concentration, implanting germanium ions and arsenic ions respectively into second regions of the first and second layers to create regions of high electron concentration, rapid thermal annealing of the device, depositing an insulating layer onto appropriate portions of the device, and depositing metalization contacts over appropriate regions for providing control gates.

Claim 3

A method of producing a germanium-gallium arsenide complementary logic transistor comprising the steps of: providing an undoped gallium arsenide substrate, growing a first layer of undoped GaAs epitaxial material on the substrate at a temperature less than 320° C., depositing a second layer of germanium by ion cluster beam processes at a temperature less than 300° C., implanting germanium ions and gallium ions into respective first regions of the second and first layers to create regions of high hole concentration, implanting germanium ions and arsenic ions respectively into the second regions of the first and second layers to create regions of high electron concentration, rapid thermal annealing of the device, depositing an insulating layer into appropriate portions of the device, and depositing metalization contacts over appropriate regions for providing control gates.

Claim 4

A method of producing a germanium-gallium arsenide complementary logic transistor comprising the steps of: providing an undoped gallium arsenide substrate, growing a first layer of undoped GaAs epitaxial material on the substrate at a temperature less than 320° C., depositing a second layer of germanium by ion cluster beam processes at a temperature less than 300° C., implanting germanium ions and gallium ions into respective first regions of the second and first layers to create regions of high hole concentration, implanting germanium ions and arsenic ions respectively into the second regions of the first and second layers to create regions of high electron concentration, rapid thermal annealing of the device, depositing an insulating layer into appropriate portions of the device, and depositing metalization contacts over appropriate regions for providing control gates.

Claim 5

A method of producing a germanium-gallium arsenide complementary logic transistor comprising the steps of: providing an undoped gallium arsenide substrate, growing a first layer of undoped GaAs epitaxial material on the substrate, depositing a second layer of undoped amorphous germanium onto the layer of undoped GaAs, implanting protons into portions of the first layer for rendering first portions of the first layer non-conducting, increasing the heat of the device to a temperature not to exceed 300° C. for crystalizing the germanium by solid phase epitaxy, implanting germanium ions and gallium ions respectively into first regions of the second and first layers proximate the non-conducting first portion to create regions of high hole concentration, implanting germanium ions and arsenic ions respectively into second regions of the first and second layers proximate other non-conducting first portions to create regions of high electron concentration, rapid thermal annealing of the device, depositing an insulating layer onto appropriate portions of the device, and depositing metalization contacts over appropriate regions for providing control gates.

Claim 6

A method of producing a germanium-gallium arsenide complementary logic transistor comprising the steps of: providing an undoped gallium arsenide substrate, growing a first layer of undoped GaAs epitaxial material on the substrate, depositing a second layer of undoped amorphous germanium onto the layer of undoped GaAs, implanting protons into portions of the first layer for rendering first portions of the first layer non-conducting, increasing the heat of the device to a temperature not to exceed 300° C. for crystalizing the germanium by solid phase epitaxy, implanting germanium ions and gallium ions respectively into first regions of the second and first layers proximate the non-conducting first portion to create regions of high hole concentration, implanting germanium ions and arsenic ions respectively into second regions of the first and second layers proximate other non-conducting first portions to create regions of high electron concentration, rapid thermal annealing of the device, depositing an insulating layer onto appropriate portions of the device, and depositing metalization contacts over appropriate regions for providing control gates.

Claim 7

A method of producing a germanium-gallium arsenide complementary logic transistor comprising the steps of: providing a high resistivity germanium substrate, depositing a first layer of GaAs onto the substrate at a temperature less than 320° C., depositing a second layer of doped GaAs onto the first layer at a temperature less than 320° C., creating first regions of p+GaAs and n+GaAs in the second layer by ion implantation and subsequent rapid thermal annealing, depositing an insulating layer disposed over appropriate portions of the first regions, and depositing metalization contacts over appropriate regions for providing control gates.

Claim 8

A method of producing a germanium-gallium arsenide complementary logic transistor comprising the steps of: providing a high resistivity germanium substrate, depositing a first layer of GaAs onto the substrate at a temperature less than 320° C., depositing a second layer of doped GaAs onto the first layer at a temperature less than 320° C., creating first regions of p+GaAs and n+GaAs in the second layer by ion implantation and subsequent rapid thermal annealing, depositing an insulating layer disposed over appropriate portions of the first regions, and depositing metalization contacts over appropriate regions for providing control gates.

Claim 9

A method of producing a germanium-gallium arsenide complementary logic transistor comprising the steps of: providing a high resistivity germanium substrate, depositing a first layer of GaAs onto the substrate at a temperature less than 320° C., depositing a second layer of doped GaAs onto the first layer at a temperature of less than 320° C., creating first regions of p+GaAs and n+GaAs in the second layer by ion implantation and subsequent rapid thermal annealing, and depositing metalization contacts over appropriate regions for providing control gates.

Claim 10

A method of producing a germanium-gallium arsenide complementary logic transistor comprising the steps of: providing a high resistivity germanium substrate, depositing a first layer of GaAs onto the substrate at a temperature less than 320° C., depositing a second layer of doped GaAs onto the first layer at a temperature of less than 320° C., creating first regions of p+GaAs and n+GaAs in the second layer by ion implantation and subsequent rapid thermal annealing, and depositing metalization contacts over appropriate regions for providing control gates.

Claim 11

A method of producing a germanium-gallium arsenide transistor comprising the steps of: providing a semi-insulating gallium arsenide substrate, growing a first layer of undoped gallium arsenide having a first predetermined level of indium, growing a second layer of gallium arsenide having a second predetermined level of indium and a predetermined level of silicon impurities, growing a third layer of undoped germanium at approximately 200° C. onto the second layer and solid phase epitaxially regrowing same, growing an insulating film of one of germanium nitride and Si--H free SiO 2 , and depositing metalization contacts over appropriate regions of the insulating layer for providing control gates.

Claim 12

A method of producing a germanium-gallium arsenide transistor comprising the steps of: providing a semi-insulating gallium arsenide substrate, growing a first layer of undoped gallium arsenide having a first predetermined level of indium, growing a second layer of gallium arsenide having a second predetermined level of indium and a predetermined level of silicon impurities, growing a third layer of undoped germanium at approximately 200° C. onto the second layer and solid phase epitaxially regrowing same, growing an insulating film of one of germanium nitride and Si--H free SiO 2 , and depositing metalization contacts over appropriate regions of the insulating layer for providing control gates.