US4558509A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating a gallium arsenide semiconductor device
Assignee: International Business Machines Corp
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Filing: 1984-06-29
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Granted: 1985-12-17
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Expires: 2004-06-29
Abstract
Abstract A method for forming a FET in a gallium arsenide substrate whereby a gate is positioned on a [100] surface of the gallium arsenide substrate in the [011] orientation, active impurities are ion implanted to form FET source and drain regions which are self-aligned with respect to the gate, and the structure is annealed subsequent to the ion implanting whereby the active impurities are caused to diffuse laterally and thereby form channel region beneath the gate.
Inventors
- 👤 Sandip Tiwari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:50
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/40; H10D62/405; H10D30/00; H10D30/80; H10D30/87; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/17; H10P32/174; H10P95/00; H10P95/90; H10P95/904
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
129 words
A method for fabricating a semiconductor device which comprises: A. providing a gallium arsenide substrate; B. providing gate regions positioned on a (100) surface of the substrate in the [011] orientation; C. ion implanting active impurities into predetermined regions of the gallium arsenide substrate to provide FET source and drain regions which are self-aligned with respect to said gate; D. annealing subsequent to ion implanting whereby the annealing temperature is greater than the ion implantation temperature whereby said active impurities are caused to diffuse laterally and thereby form channel region beneath said gate; E. delineating contact holes to said gate and to source and drain regions; and F. depositing and delineating metallic-type high conductively electrical interconnection pattern that makes electrical connection to the gate and to source and drain.
Claim 2
Independent Claim
129 words
A method for fabricating a semiconductor device which comprises: A. providing a gallium arsenide substrate; B. providing gate regions positioned on a (100) surface of the substrate in the [011] orientation; C. ion implanting active impurities into predetermined regions of the gallium arsenide substrate to provide FET source and drain regions which are self-aligned with respect to said gate; D. annealing subsequent to ion implanting whereby the annealing temperature is greater than the ion implantation temperature whereby said active impurities are caused to diffuse laterally and thereby form channel region beneath said gate; E. delineating contact holes to said gate and to source and drain regions; and F. depositing and delineating metallic-type high conductively electrical interconnection pattern that makes electrical connection to the gate and to source and drain.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein said active impurities are N-type impurities.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein the length of the gate is about 1.5 microns or less.
Claim 5
Dependent Claim
17 words
The method of claim 1 wherein the gate length is about 0.5 microns to about 1 micron.
Claim 6
Dependent Claim
30 words
The method of claim 1 wherein the annealing is carried out at a temperature of about 750° C. to about 1100° C. for about 2 seconds to about 180 minutes.
Claim 7
Dependent Claim
12 words
The method of claim 1 wherein said substrate is a semi-insulating substrate.
Claim 8
Dependent Claim
30 words
The method of claim 1 wherein said substrate is a gallium arsenide substrate containing active impurities of a type different from the active impurities for said source and drain regions.
Claim 9
Dependent Claim
20 words
The method of claim 2 wherein said N-type impurities are selected from the group of sulphur, silicon, selinium, and telurium.
Claim 10
Dependent Claim
11 words
The method of claim 2 wherein said N-type impurities are sulphur.
Claim 11
Dependent Claim
17 words
The method of claim 3 wherein the gate length is about 0.2 microns to about 1.5 microns.
Claim 12
Dependent Claim
37 words
The method of claim 9 wherein the N-type impurities are ion implanted employing energy of about 30 KeV to about 200 KeV at a dose of about 1.5×10 12 to about 5×10 14 per cm 2 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-16 | 1989-06-17 | 1989-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-16 | 1993-06-17 | 1993-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-16 | 1997-06-17 | 1997-12-17 | $7700.00 | Window Closed / Lapsed |