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US4396437A Expired / Lapsed US ⏱️ 0.0 years remaining

Selective encapsulation, controlled atmosphere annealing for III-V semiconductor device fabrication

Assignee: Raytheon Co
•
Filing: 1981-05-04
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Granted: 1983-08-02
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Expires: 2001-05-04
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Abstract

Abstract A post-ion implantation annealing technique is provided to remove implantation damage in the active region of III-V (e.g., GaAs) semiconductor devices formed in a III-V semi-insulating substrate and separated by a field region. The technique involves applying a dielectric encapsulation selectively over the device active area and annealing in a controlled reducing atmosphere which includes the Group V element (e.g., arsenic). The dielectric encapsulant over the active region permits migration of the species employed to render the substrate semi-insulating (e.g., Cr in GaAs substrates), thereby resulting in high carrier mobility in the active region. Without encapsulation, migration of the species in the field region is substantially suppressed, thereby resulting in good inter-device isolation.

Inventors

  • 👤 Siang P. Kwok
  • 👤 Milton Feng
  • 👤 Victor K. Eu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 07:34
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/90; H10P95/904

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 95 words
A process for fabricating III-V semiconductor devices having an active region formed on a III-V substrate rendered semi-insulating by a species, said process including at least one ion implantation step, wherein the improvement includes removing implantation damage by the following steps: (a) forming a layer of dielectric material over said active region, said dielectric material capable of gettering of said species; and (b) annealing the partially coated substrate in a reducing atmosphere including said Group V element at a temperature and for a time sufficient to substantially remove all implantation damage in said active region.
Claim 2
Dependent Claim 95 words
A process for fabricating III-V semiconductor devices having an active region formed on a III-V substrate rendered semi-insulating by a species, said process including at least one ion implantation step, wherein the improvement includes removing implantation damage by the following steps: (a) forming a layer of dielectric material over said active region, said dielectric material capable of gettering of said species; and (b) annealing the partially coated substrate in a reducing atmosphere including said Group V element at a temperature and for a time sufficient to substantially remove all implantation damage in said active region.
Claim 3
Dependent Claim 17 words
The process of claim 1 in which said III-V substrate comprises GaAs and said species comprises Cr.
Claim 4
Dependent Claim 29 words
The process of claim 2 in which said reducing atmosphere includes arsenic, whose partial pressure is effective to avoid depletion of Cr near the surface of said III-V substrate.
Claim 5
Dependent Claim 17 words
The process of claim 3 in which said reducing atmosphere comprises a mixture of hydrogen and arsenic.
Claim 6
Dependent Claim 17 words
The process of claim 1 in which said III-V substrate comprises InP and said species comprises Fe.
Claim 7
Dependent Claim 27 words
The process of claim 1 in which said dielectric material is selected form the group consisting of SiO 2 , Si 3 N 4 and mixtures thereof.
Claim 8
Dependent Claim 20 words
The process of claim 6 in which the thickness of said dielectric material ranges from about 50 to 3,000 A.
Claim 9
Dependent Claim 16 words
The process of claim 7 in which said thickness ranges from about 1,000 to 2,000 A.
Claim 10
Dependent Claim 26 words
The process of claim 1 in which said annealing is performed at a temperature between about 800° and 900° C. for about 20 to 40 minutes.

References Cited (Backward Citations)

US3984263A Cited
US4058413A Cited
US4327475A Cited
US4312681A Cited
US4357180A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-08-01 1987-01-31 1987-08-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-08-01 1991-01-31 1991-08-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-08-01 1995-01-31 1995-08-02 $7700.00 Window Closed / Lapsed

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