Enhanced mobility buried channel transistor structure

Claim 2

An enhanced mobility buried channel transistor structure comprising a semi-insulating gallium arsenide substrate having a pair of opposed surfaces; an undoped layer of gallium arsenide deposited upon one of said surfaces of said substrate; a first layer of undoped Al x Ga 1-x As deposited on said undoped layer of gallium arsenide, where the value of x varies through said first layer, from a maximum value distant from said undoped layer to a minimum proximal to said undoped layer; a second layer of undoped Al x' Ga 1-x' As deposited onto said first layer, where the value of x' for said second layer is a constant; a doped layer of Al x" Ga 1-x "As deposited onto said second layer, wherein the value of x" for said doped layer is a constant; a source electrode deposited onto said doped layer; a drain electrode deposited onto said doped layer; and a gate electrode deposited onto said doped layer, between said source electrode and said drain electrode.

Claim 3

The structure as recited in claim 1 wherein said constants and said maximum value are equal to each other, wherein said minimum is zero, and wherein said value of x through said first layer uniformly varies with distance from said undoped layer of gallium arsenide.

Claim 4

The structure as recited in claim 1 wherein said maximum value and said constants are equal.

Claim 5

The structure as recited in claim 1 wherein the thickness of said doped layer is on the order of 250 to 1000 angstroms, the thickness of said second layer is on the order of 0 to 100 angstroms, and the thickness of said first layer is on the order of 100 to 200 angstroms.

Claim 6

An enhanced mobility buried channel transistor structure comprising a semi-insulating substrate formed of a III-V semiconducting compound, having a pair of opposed surfaces; an undoped layer of said compound deposited upon one of said surfaces of said substrate; a first layer of an undoped compound formed of said III-V compound and a variable proportion of an element from Group III of the Periodic Table deposited on said undoped layer, where the proportion of said element varies through said first layer, from a maximum value distant from said undoped layer to a minimum proximal to said undoped layer; a second layer of an undoped compound formed of III-V ternary or quaternary compound and said maximum proportion of said element, deposited on said first layer; a doped layer of said last named compound formed of said III-V ternary or quaternary compound and said maximum proportion of said element, deposited onto said second layer; a source electrode deposited onto said doped layer; a drain electrode deposited onto said doped layer; and a gate electrode deposited onto said doped layer, between said source electrode and said drain electrode.

Claim 7

An enhanced mobility buried channel transistor structure comprising a semi-insulating substrate formed of a III-V semiconducting compound, having a pair of opposed surfaces; an undoped layer of said compound deposited upon one of said surfaces of said substrate; a first layer of an undoped compound formed of said III-V compound and a variable proportion of an element from Group III of the Periodic Table deposited on said undoped layer, where the proportion of said element varies through said first layer, from a maximum value distant from said undoped layer to a minimum proximal to said undoped layer; a second layer of an undoped compound formed of III-V ternary or quaternary compound and said maximum proportion of said element, deposited on said first layer; a doped layer of said last named compound formed of said III-V ternary or quaternary compound and said maximum proportion of said element, deposited onto said second layer; a source electrode deposited onto said doped layer; a drain electrode deposited onto said doped layer; and a gate electrode deposited onto said doped layer, between said source electrode and said drain electrode.