High electron mobility semiconductor device

Claim 2

A semiconductor device having: a first single crystalline semiconductor layer (12); a second single crystalline semiconductor layer having an electron affinity different from that of the first single crystalline semiconductor layer; a heterojunction between the first and second single crystalline semiconductor layers; an electron-storing layer (18) for forming a conduction channel, formed in proximity to the heterojunction due to the difference in electron affinity; and a gate electrode for controlling the concentration of quasi two-dimensional electron gas in the conduction channel; characterized in that an additional semiconductor layer (17) having a semiconductor different from that of the second single crystalline layer (13) is formed at least on a part of the second single crystalline layer (13) in the neighborhood (17A') of the gate electrode (16).

Claim 3

A semiconductor device according to claim 1, wherein said additional semiconductor layer (17) extends from the neighborhood (17A') of the gate electrode (16) to the top of the gate electrode (16).

Claim 4

A semiconductor device according to claim 1 or 2, wherein part of said additional semiconductor layer (17) is formed or interposed between the gate electrode (16) and the second single crystalline semiconductor layer (13), and the thickness of the additional semiconductor layer (17) beneath the gate electrode (16) is smaller than that of the additional semiconductor layer (17) in the neighborhood (17A') of the gate electrode (16).

Claim 5

A semiconductor device according to any one of claims 1 through 3, wherein an intermediate layer ('21) is formed between said second single crystalline semiconductor layer (13) and said additional semiconductor layer (17), and the main composition of said intermediate layer (21) is' identical to that of the second single crystalline semiconductor layer (13) at its bottom surface, while the main composition of said intermediate layer (21) is identical to that of said additional semiconductor layer at its top surface.

Claim 6

A semiconductor device according to claim 4, wherein the rate of change of the main composition in said intermediate layer (21) in the growth direction is gradual.

Claim 7

A semiconductor device according to any one of claims 1 through 5, wherein said additional semiconductor layer (17) is provided with a groove which selectively exposes the top surface of the underlying single crystalline semiconductor layer (13, 21), and the gate electrode (16) is formed in said groove.

Claim 8

A semiconductor device according to any one of claims 1 through 6, wherein said additional semiconductor layer (17) is present not only in a first part of the semiconductor device where a normally off-type transistor (HEM T ) is to be formed but also in a second part of the semiconductor device where a normally on-type transistor (HEMT) is to be formed.

Claim 9

A semiconductor device according to any one of claims 1 through 7, wherein said first single crystalline semiconductor layer= (12) is mainly composed of GaAs, said second single crystalline semiconductor layer (13) is mainly composed of AlGaAs, and said additional single crystalline semiconductor layer (17) is mainly composed of GaAs.

Claim 10

A process for producing a semiconductor device having: a first single crystalline semiconductor layer (12); (13) a second single crystalline semiconductor layer/having an electron affinity different from that of the first single crystalline semiconductor layer; a heterojunction between the first and second single crystalline semiconductor layers; an electron-storing layer (18) serving as a conduction channel formed in proximity to the heterojunction due to the difference in electron affinity; and a gate electrode (16) for controlling the concentration of quasi two-dimensional electron gas in the conduction channel; characterized in that subsequent to the formation of said second single crystalline semiconductor layer (13) on said first single crystalline semiconductor layer (12), an additional semiconductor layer (17) having a semiconductor different from that of the second single crystalline layer (13) is formed on at least part of the second single crystalline layer (13) in the neighborhood (17A') of the gate electrode (16) and said additional semiconductor layer (17) is selectively etched so as to expose an underlying single crystalline semiconductor layer (13, 21) and a gate electrode (16) is subsequently formed on the exposed part of the underlying single crystalline semiconductor layer.

Claim 11

A process for producing a semiconductor device having: a first single crystalline semiconductor layer (12); (13) a second single crystalline semiconductor layer/having an electron affinity different from that of the first single crystalline semiconductor layer; a heterojunction between the first and second single crystalline semiconductor layers; an electron-storing layer (18) serving as a conduction channel formed in proximity to the heterojunction due to the difference in electron affinity; and a gate electrode (16) for controlling the concentration of quasi two-dimensional electron gas in the conduction channel; characterized in that subsequent to the formation of said second single crystalline semiconductor layer (13) on said first single crystalline semiconductor layer (12), an additional semiconductor layer (17) having a semiconductor different from that of the second single crystalline layer (13) is formed on at least part of the second single crystalline layer (13) in the neighborhood (17A') of the gate electrode (16) and said additional semiconductor layer (17) is selectively etched so as to expose an underlying single crystalline semiconductor layer (13, 21) and a gate electrode (16) is subsequently formed on the exposed part of the underlying single crystalline semiconductor layer.

Claim 12

A process for producing a semiconductor device having: a first single crystalline semiconductor layer (12); (13) a second single crystalline semiconductor layer/having an electron affinity different from that of the first single crystalline semiconductor layer; a heterojunction between the first and second single crystalline semiconductor layers; (18) an electron-storing layer serving as a conduction channel formed in proximity to the heterojunction due to the difference in electron affinity; and a gate electrode (16) for controlling the concentration of quasi two-dimensional electron gas in the conduction channel; characterized in that said process comprises, after the formation of said gate electrode (16), the step of carrying out the crystal growth of an additional semiconductor layer (17) extending from the top surface of an underneath semiconductor layer (13, 17c, 21) onto the gate electrode (16).

Claim 13

A process for producing a semiconductor device having: a first single crystalline semiconductor layer (12); (13) a second single crystalline semiconductor layer/having an electron affinity different from that of the first single crystalline semiconductor layer; a heterojunction between the first and second single crystalline semiconductor layers; (18) an electron-storing layer serving as a conduction channel formed in proximity to the heterojunction due to the difference in electron affinity; and a gate electrode (16) for controlling the concentration of quasi two-dimensional electron gas in the conduction channel; characterized in that said process comprises, after the formation of said gate electrode (16), the step of carrying out the crystal growth of an additional semiconductor layer (17) extending from the top surface of an underneath semiconductor layer (13, 17c, 21) onto the gate electrode (16).