Self-aligned process for fabricating gallium arsenide metal-semiconductor field effect transistors

Claim 1

In a method for fabricating a field effect transistor (FET) wherein a pair of diffusion sources are disposed on a semiconductor layer, and are spaced apart by a first distance, the steps of: forming on said diffusion sources and, surrounding said diffusion sources at the peripheries thereof with insulation to provide an exposed region of said semiconductor layer between said diffusion sources, thereby defining a gate area having the length of said gate area less than said first distance; driving said diffusion sources to provide a pair of doped regions in said semiconductor layer forming the source and drain of said FET, which source and drain, as a result of out-diffusion in the lateral direction, are spaced apart by a distance less than said first distance but greater than the length of said gate area; and removing said diffusion sources to provide additional exposed regions of said semicondutor layer over said source and drain, all of said exposed regions being surrounded by insulation.

Claim 10

A method for fabricating a metal semiconductor field effect transistor (MESFET) comprising the steps of: providing a structure comprising a semi-insulating substrate having a first lightly doped layer of a first conductivity type and having thereon a second heavily doped layer of said first conductivity type; defining on said structure a field region and a transistor region having a gate region between a source region and a drain region; etching selectively to remove said first and second layers exposing said substrate in said field region, and removing said second layer in said gate region within said transistor region; forming a dielectric layer over said structure; forming the source and drain of said MESFET by driving selectively the dopants from said second layer to said first layer in said source and drain regions using said second layer as diffusion sources; etching directionally to remove substantially said dielectric layer in said gate region exposing said substrate, and leaving side walls of said dielectric layer on the sides of said source and drain regions; removing said second layer in said source and drain regions exposing the source and the drain of said MESFET; and depositing a metal layer onto said structure to form the gate of said MESFET and to make electrical contacts with the source and drain of said MESFET having isolations provided by said dielectric side walls.

Claim 11

A method for fabricating a metal semiconductor field effect transistor (MESFET) comprising the steps of: providing a structure comprising a semi-insulating substrate having a first lightly doped layer of a first conductivity type and having thereon a second heavily doped layer of said first conductivity type; defining on said structure a field region and a transistor region having a gate region between a source region and a drain region; etching selectively to remove said first and second layers exposing said substrate in said field region, and removing said second layer in said gate region within said transistor region; forming a dielectric layer over said structure; forming the source and drain of said MESFET by driving selectively the dopants from said second layer to said first layer in said source and drain regions using said second layer as diffusion sources; etching directionally to remove substantially said dielectric layer in said gate region exposing said substrate, and leaving side walls of said dielectric layer on the sides of said source and drain regions; removing said second layer in said source and drain regions exposing the source and the drain of said MESFET; and depositing a metal layer onto said structure to form the gate of said MESFET and to make electrical contacts with the source and drain of said MESFET having isolations provided by said dielectric side walls.

Claim 21

A method for fabricating a self-aligned metal semiconductor field effect transistor (MESFET) comprising the steps of: providing a structure comprising a semi-insulating substrate having a first lightly doped layer of a first conductivity type and having thereon a second heavily doped layer of said first conductivity type; applying a first photoresist layer onto said structure; exposing and devloping selectively said first photoresist layer to provide a patterned opening defining a transistor region and a field region; etching selectively to remove said second layer and said first layer underneath said second layer in said field region exposing said semi-insulating substrate; applying a second photoresist layer onto said structure; exposing and developing said second photoresist layer to provide a patterned opening defining a gate region within said transistor region; etching selectively said gate region to remove said second layer, and forming two mesas having said gate region therebetween; forming a dielectric layer over said structure; forming the source and drain of said MESFET by driving selectively the dopants from said second layer to said first layer in the regions of said two mesas using said second layer as diffusion sources; etching directionally using reactive ion etching to remove substantially said dielectric layer in said gate region exposing said substrate, and leaving side walls of dielectric layer on the sides of said two mesas; removing said second layer in said two mesas exposing the source and drain of said MESFET; and depositing a metal layer onto said structure to form the gate of said MESFET, and to make electrical contacts with the drain and source of said MESFET having isolations of the drain, source and gate provided by said dielectric side walls.

Claim 22

A method for fabricating a self-aligned metal semiconductor field effect transistor (MESFET) comprising the steps of: providing a structure comprising a semi-insulating substrate having a first lightly doped layer of a first conductivity type and having thereon a second heavily doped layer of said first conductivity type; applying a first photoresist layer onto said structure; exposing and devloping selectively said first photoresist layer to provide a patterned opening defining a transistor region and a field region; etching selectively to remove said second layer and said first layer underneath said second layer in said field region exposing said semi-insulating substrate; applying a second photoresist layer onto said structure; exposing and developing said second photoresist layer to provide a patterned opening defining a gate region within said transistor region; etching selectively said gate region to remove said second layer, and forming two mesas having said gate region therebetween; forming a dielectric layer over said structure; forming the source and drain of said MESFET by driving selectively the dopants from said second layer to said first layer in the regions of said two mesas using said second layer as diffusion sources; etching directionally using reactive ion etching to remove substantially said dielectric layer in said gate region exposing said substrate, and leaving side walls of dielectric layer on the sides of said two mesas; removing said second layer in said two mesas exposing the source and drain of said MESFET; and depositing a metal layer onto said structure to form the gate of said MESFET, and to make electrical contacts with the drain and source of said MESFET having isolations of the drain, source and gate provided by said dielectric side walls.

Claim 31

A method for fabricating a self-aligned metal semiconductor field effect transistor (MESFET) comprising the steps of: forming a first lightly doped layer of a first conductivity type onto a semi-insulating substrate; forming a second heavily doped layer of said first conductivity type onto said first layer to form a production structure; applying a first photoresist layer onto said structure; exposing and developing selectively said first photoresist layer to provide a patterned opening defining a transistor region and a field region; etching selectively to remove said second layer and said first layer underneath said second layer in said field region exposing said semi-insulating substrate; applying a second photoresist layer onto said structure; exposing and developing said second photoresist layer to provide a patterned opening defining a gate region within said transistor region; etching selectively said gate region to remove said second layer, and forming two mesas having said gate region therebetween; forming a dielectric layer over said structure; forming the source and drain of said MESFET by driving selectively the dopants from said second layer to said first layer in the regions of said two mesas using said second layer as diffusion sources; etching directionally using reactive ion etching to remove substantially said dielectric layer in said gate region exposing said substrate, and leaving side walls of dielectric layer on the sides of said two mesas; removing said second layer in said two mesas exposing the source and drain of said MESFET; and depositing a metal layer onto said structure to form the gate of said MESFET, and to make electrical contacts with the drain and source of said MESFET having isolations of the drain, source and gate provided by said dielectric side walls.

Claim 32

A method for fabricating a self-aligned metal semiconductor field effect transistor (MESFET) comprising the steps of: forming a first lightly doped layer of a first conductivity type onto a semi-insulating substrate; forming a second heavily doped layer of said first conductivity type onto said first layer to form a production structure; applying a first photoresist layer onto said structure; exposing and developing selectively said first photoresist layer to provide a patterned opening defining a transistor region and a field region; etching selectively to remove said second layer and said first layer underneath said second layer in said field region exposing said semi-insulating substrate; applying a second photoresist layer onto said structure; exposing and developing said second photoresist layer to provide a patterned opening defining a gate region within said transistor region; etching selectively said gate region to remove said second layer, and forming two mesas having said gate region therebetween; forming a dielectric layer over said structure; forming the source and drain of said MESFET by driving selectively the dopants from said second layer to said first layer in the regions of said two mesas using said second layer as diffusion sources; etching directionally using reactive ion etching to remove substantially said dielectric layer in said gate region exposing said substrate, and leaving side walls of dielectric layer on the sides of said two mesas; removing said second layer in said two mesas exposing the source and drain of said MESFET; and depositing a metal layer onto said structure to form the gate of said MESFET, and to make electrical contacts with the drain and source of said MESFET having isolations of the drain, source and gate provided by said dielectric side walls.