Fabrication of metal insulator semiconductor field effect transistors

Abstract

Abstract A PROCESS OF FABRICATING A MISFET IN WHICH A PAIR OF SPACED APART DOPED SILICON DIOXIDE BODIES IS FORMED ON THE SURFACE OF A SILICON SUBSTRATE. A LAYER OF SILCON NITRIDE IS FORMED OVER THE SURFACE OF THE BODIES AND THE SUBSTRATE AND THE PORTION OF THE LAYERS IN THE SPACE BETWEEN THE BLOCKS IS REMOVED. A THIN LAYER OF THE SILCON SUBSTRATE IS THEN REMOVED FROM THE SPACE BETWEEN THESE BODIES AND A RELATIVELY THIN SILICON DIOXIDE LAYER IS FORMED ON THE SILICON SUBSTRATE IN THIS SPACE. A SECOND LAYER OF SILICON NITRIDE IS THEN FORMED OVER THE FIRST SILICON NITRIDE LAYER AND THE SILICON DIOXIDE LAYER THEREBY TO FORM A DIELECTRIC REGION FOR THE GATE OF THE TRANSISTOR. THEREAFTER SOURCE AND DRAIN REGIONS ARE FORMED BY DIFFUSING IMPURTIES FROM THE DOPED SILICON BLOCKS INTO UNDERLYING PORTIONS OF THE SILICON SUBSTRATE THEREBY FORMING SOURCE AND DRAIN REGIONS, THE SILICON NITRIDE LAYERS PREVENTING OUT-DIFFUSION OF THE DOPANT FROM THE DOPED BODIES AND THE SECOND SILICON NITRIDE LAYER COVERING ANY GAPS BETWEEN THE SILICON DIOXIDE LAYER IN THE GATE REGION BETWEEN THE SILCON DIOXIDE LAYER AND THE FIRST SILICON LAYER.

Inventors

• 👤 George A Brown

Bibliographic Details