Configurable inputs and outputs for memory stacking system and method

Claim 2

A memory device comprising: a first die comprising: a first circuit configured to be enabled by a first control signal; a first input pin configured to receive the first control signal; and a first path selector arranged between the first input pin and the first circuit and configured to select a first signal path to the first circuit from the first input pin; and a second die comprising: a second circuit configured to be enabled by a second control signal; a second input pin configured to receive the second control signal; and a second path selector arranged between the second input pin and the second circuit and configured to select a second signal path to the second circuit from the second input pin, wherein the first die and the second die form a stack such that a signal may be routed though each of the first signal path and the second signal path in a direction perpendicular to a surface of the first die and a surface of the second die, wherein the surface of the second die is disposed parallel to the surface of the first die.

Claim 3

The memory device of claim 1 , wherein the first control signal is a chip select signal.

Claim 4

The memory device of claim 1 , wherein the first path selector comprises a multiplexer.

Claim 5

The memory device of claim 1 , comprising a path selector control circuit comprising a fuse, wherein the path selector control circuit is configured to control the first path selector.

Claim 6

The memory device of claim 4 , wherein the path selector control circuit is configured to provide a high signal when the fuse is blown.

Claim 7

The memory device of claim 4 , wherein the path selector control circuit is configured to provide a low signal when an antifuse is blown.

Claim 8

The memory device of claim 1 , comprising memory comprising a plurality of die.

Claim 9

A memory module comprising: a die stack comprising a plurality of memory devices; a plurality of pins disposed within the plurality of memory devices, wherein each of the plurality of pins is configured to receive a signal; a plurality of circuits disposed within each of the plurality of memory devices; and a plurality of path selectors configured to selectively provide signal paths between the plurality of pins and the plurality of circuits, wherein a plurality of signals may be routed through the signal paths such that each of the plurality of signals enters the die stack from pins selected from the plurality of pins, the pins being disposed on a bottom surface of the die stack and each of the plurality of signals routing upward through the signal paths in a direction perpendicular to the bottom surface.

Claim 10

A memory module comprising: a die stack comprising a plurality of memory devices; a plurality of pins disposed within the plurality of memory devices, wherein each of the plurality of pins is configured to receive a signal; a plurality of circuits disposed within each of the plurality of memory devices; and a plurality of path selectors configured to selectively provide signal paths between the plurality of pins and the plurality of circuits, wherein a plurality of signals may be routed through the signal paths such that each of the plurality of signals enters the die stack from pins selected from the plurality of pins, the pins being disposed on a bottom surface of the die stack and each of the plurality of signals routing upward through the signal paths in a direction perpendicular to the bottom surface.

Claim 11

The memory module of claim 8 , wherein the memory module comprises a dual inline memory module (DIMM).

Claim 12

The memory module of claim 8 , wherein each of the plurality of memory devices comprises a dynamic random access memory (DRAM) device.

Claim 13

The memory module of claim 8 , wherein the plurality of signals include a chip select signal, a clock enable signal, an on-die termination signal, and a calibration signal.

Claim 14

The memory module of claim 8 , wherein the plurality of path selectors comprises at least one multiplexer.

Claim 15

The memory module of claim 8 , wherein the plurality of path selectors comprises at least one path selector control circuit comprising a fuse or antifuse, wherein the path selector control circuit is configured to control the path selector.

Claim 16

The memory module of claim 13 , wherein the path selector control circuit is configured to provide a high signal when the fuse is blown.

Claim 17

The memory module of claim 13 , wherein the path selector control circuit is configured to provide a low signal when the antifuse is blown.

Claim 18

A computer system comprising: a processor; and a memory system coupled to the processor and comprising: a memory controller; a memory device comprising a die stack; a first circuit in a first die of the die stack and a second circuit in a second die of the die stack, wherein the first and second circuits are configured to be enabled by a control signal; a first input pin disposed within the first die on a bottom surface of the die stack, the first input pin configured to receive the control signal; a first path selector arranged between the first input pin and the first circuit and configured to select a first signal path to the first circuit from the first input pin based on the control signal; and a second input pin disposed within the second die in a position in-line with and above the first input pin, the second input pin configured to receive the control signal; a second path selector arranged between the second input pin and the second circuit and configured to select a second signal path to the second circuit from the second input pin based on the control signal such that a signal may be routed though each of the first signal path and the second signal path in a direction perpendicular to the bottom surface of the die stack.

Claim 19

A computer system comprising: a processor; and a memory system coupled to the processor and comprising: a memory controller; a memory device comprising a die stack; a first circuit in a first die of the die stack and a second circuit in a second die of the die stack, wherein the first and second circuits are configured to be enabled by a control signal; a first input pin disposed within the first die on a bottom surface of the die stack, the first input pin configured to receive the control signal; a first path selector arranged between the first input pin and the first circuit and configured to select a first signal path to the first circuit from the first input pin based on the control signal; and a second input pin disposed within the second die in a position in-line with and above the first input pin, the second input pin configured to receive the control signal; a second path selector arranged between the second input pin and the second circuit and configured to select a second signal path to the second circuit from the second input pin based on the control signal such that a signal may be routed though each of the first signal path and the second signal path in a direction perpendicular to the bottom surface of the die stack.

Claim 20

The memory system of claim 16 , wherein the memory device comprises a dynamic random access memory (DRAM) device.

Claim 21

The memory system of claim 16 , wherein the control signal comprises a chip select signal.

Claim 22

The memory system of claim 16 , wherein the control signal comprises an inverse chip select signal.

Claim 23

The memory system of claim 16 , wherein the first path selector comprises a fuse controlled path selector.

Claim 24

The memory system of claim 20 , wherein the fuse controlled path selector includes an antifuse.

Claim 27

The method of claim 22 , comprising configuring the plurality of memory die in the stack without providing a redistribution layer.

Claim 28

The memory module of claim 8 , wherein each of the plurality of circuits is configured to be enabled by control signals, the control signals communicatively coupling the path selectors between the plurality of pins and the plurality of circuits.

Claim 29

The memory module of claim 8 , wherein the memory devices include four ×8 devices configurable as two ranks of ×16 memory stacked on a single side of the memory module.