US5332922A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-chip semiconductor package
Assignee: Micron Memory Japan Ltd
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Filing: 1991-04-26
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Granted: 1994-07-26
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Expires: 2011-04-26
Abstract
Abstract A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
Inventors
- 👤 Satoshi Oguchi
- 👤 Masamichi Ishihara
- 👤 Kazuya Ito
- 👤 Gen Murakami
- 👤 Ichiro Anjoh
- 👤 Toshiyuki Sakuta
- 👤 Yasunori Yamaguchi
- 👤 Yasuhiro Kasama
- 👤 Tetsu Udagawa
- 👤 Eiji Miyamoto
- 👤 Youichi Matsuno
- 👤 Hiroshi Satoh
- 👤 Atsusi Nozoe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:53
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; G11C5/06; H; H10; H10B; H10B12/00; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W70/421; H10W70/442; H10W72/00; H10W72/90; H10W90/00; H10W90/811; H10W72/20; H10W72/29; H10W72/50; H10W72/521; H10W72/522; H10W72/541; H10W72/5445; H10W72/5449; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/5525; H10W72/553; H10W72/555; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/874; H10W72/884; H10W72/931; H10W72/932; H10W72/941; H10W72/944; H10W72/9445; H10W74/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/753; H10W90/756
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
224 words
A semiconductor device comprising: a first and a second semiconductor chip each having a plurality of external terminals arranged in a row centrally of a main surface thereof, and said first and said second semiconductor chips having same function; a body for sealing said first and second semiconductor chips; a plurality of leads disposed in said body and protruding from said body, each of said plurality of leads having a first branch lead and a second branch lead; and a plurality of first wires each one thereof electrically connecting a first end of a respective said first branch lead to one of said external terminals on said first semiconductor chip, and a plurality of second wires each one thereof electrically connecting a first end of a respective said second branch lead to one of said external terminals on said second semiconductor chip, wherein the main surface of said first and said second semiconductor chips are disposed in an opposing relation to each other, wherein each one of said plurality of leads includes a mutual connection of a second, opposing end of a corresponding said first branch lead and a second, opposing end of a corresponding said second branch lead, and wherein said first and second branch leads and mutual connections thereof corresponding to each of said plurality of leads are disposed within said body.
Claim 2
Dependent Claim
224 words
A semiconductor device comprising: a first and a second semiconductor chip each having a plurality of external terminals arranged in a row centrally of a main surface thereof, and said first and said second semiconductor chips having same function; a body for sealing said first and second semiconductor chips; a plurality of leads disposed in said body and protruding from said body, each of said plurality of leads having a first branch lead and a second branch lead; and a plurality of first wires each one thereof electrically connecting a first end of a respective said first branch lead to one of said external terminals on said first semiconductor chip, and a plurality of second wires each one thereof electrically connecting a first end of a respective said second branch lead to one of said external terminals on said second semiconductor chip, wherein the main surface of said first and said second semiconductor chips are disposed in an opposing relation to each other, wherein each one of said plurality of leads includes a mutual connection of a second, opposing end of a corresponding said first branch lead and a second, opposing end of a corresponding said second branch lead, and wherein said first and second branch leads and mutual connections thereof corresponding to each of said plurality of leads are disposed within said body.
Claim 3
Dependent Claim
41 words
A semiconductor device according to claim 1, further comprising an insulating film interposed between said first branch leads, respectively, and said first semiconductor chip, and a further insulating film interposed between said second branch leads, respectively, and said second semiconductor chip.
Claim 4
Dependent Claim
15 words
A semiconductor device according to claim 2, wherein said body is formed of a resin.
Claim 5
Dependent Claim
15 words
A semiconductor device according to claim 1, wherein said body is formed of a resin.
Claim 6
Dependent Claim
20 words
A semiconductor device according to claim 4, wherein each of said first and second semiconductor chips is a memory chip.
Claim 7
Dependent Claim
33 words
A semiconductor device according to claim 4, wherein said first and second semiconductor chips are memory chips of a memory package and are activated simultaneously and execute storage data inputting/outputting operation in parallel.
Claim 8
Dependent Claim
49 words
A semiconductor device according to claim 4, wherein said first and second semiconductor chips are memory chips of a memory package and are designed selectively in accordance with a predetermined chip selection signal commonly applied to a respective external terminal of each of said first and second semiconductor chips.
Claim 9
Dependent Claim
42 words
A semiconductor device according to claim 7, wherein said memory package and said memory chips are based on an address multiplex system in which a row address signal and a column address signal are inputted time-sharingwise through a common address input terminal.
Claim 10
Dependent Claim
52 words
A semiconductor device according to claim 7, wherein said chip selection signal is fed as part of a row address signal, and a word line selecting operation of said first and second memory chips is substantially executed selectively in accordance with said chip selection signal whereby the memory chips are activated selectively.
Claim 11
Dependent Claim
31 words
A semiconductor device according to claim 9, wherein a row address signal decoding operation of said first and second memory chips is executed selectively in accordance with said chip selection signal.
Claim 12
Dependent Claim
45 words
A semiconductor device according to claim 7, wherein said chip selection signal is fed as part of a column address signal, and the first and second memory chips are activated simultaneously and execute storage data inputting/outputting operation selectively in accordance with said chip selection signal.
Claim 13
Dependent Claim
41 words
A semiconductor device according to claim 11, further comprising an insulating film interposed between said first branch leads, respectively, and said first semiconductor chip, and a further insulating film interposed between said second branch leads, respectively, and said second semiconductor chip.
Claim 14
Dependent Claim
68 words
A semiconductor device according to claim 12, wherein said first and second semiconductor chips are rectangular shaped and the mutual connections of respective ones of said first and second branch leads are extended outwardly as single leads along respective ones of a pair of longer edge sides of said first and second semiconductor chips and said single leads protrude, respectively, through corresponding outer, opposing walls of said body.
Claim 15
Dependent Claim
31 words
A semiconductor device according to claim 13, wherein said external terminals are disposed in a direction parallel to said pair of longer edge sides of said first and second semiconductor chips.
Claim 16
Dependent Claim
68 words
A semiconductor device according to claim 4, wherein said first and second semiconductor chips are rectangular shaped and the mutual connections of respective ones of said first and second branch leads are extended outwardly as single leads along respective ones of a pair of longer edge sides of said first and second semiconductor chips and said single leads protrude, respectively, through corresponding outer, opposing walls of said body.
Claim 17
Dependent Claim
31 words
A semiconductor device according to claim 15, wherein said external terminals are disposed in a direction parallel to said pair of longer edge sides of said first and second semiconductor chips.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-25 | 2006-01-24 | 2006-07-26 | $7700.00 | Window Closed / Lapsed |