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JPS63136642A Expired / Lapsed JP ⏱️ 0.0 years remaining

2-layer type semiconductor integrated circuit

Assignee: Dai Nippon Printing Co Ltd
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Filing: 1986-11-28
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Granted: —
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Expires: 2006-11-28
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Abstract

Abstract PURPOSE:To obtain a 2-layer structure in which IC chips are easily laminated, IC chips are easily laminated and connected at their bonding pads and external lead electrodes by providing as a bonding intermediate layer finger lead ends between two types of IC chips disposed at upper and lower positions. CONSTITUTION:A metal foil is laminated through an adhesive layer 15 on a heat resistant insulating film 11 having a rectangular opening for disposing IC chips 14a and 14b, and external lead electrodes are provided on a film carrier tape by a photolithography method. Bumps 13a, 13b are provided by plating or etching on both front and rear surfaces of the end of the lead 12, and the bumps are bonded to bonding pads 15a, 15b. A plurality of finger lead ends are disposed to be interposed between elevationally opposed IC chips 14a and 14b. The chips 14a and 14b can be laminated through the plurality of finger lead ends.

Inventors

  • 👤 Hideji Sagara
  • 👤 秀次 相楽

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 11:10
CPC Classifications
H; H10; H10W; H10W72/00

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