← Back to Patent Explorer
US5705938A Expired / Lapsed US ⏱️ 0.0 years remaining

Programmable switch for FPGA input/output signals

Assignee: Xilinx Inc
•
Filing: 1995-09-05
•
Granted: 1998-01-06
•
Expires: 2015-09-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A programmable switch for a field programmable gate array (FPGA) allows a user to reconfigure or partly reconfigure the FPGA from within the FPGA, allows an addressable configuration memory to be addressed through a set of pins for configuration and through user logic for reconfiguration. The same pins can be used for both configuration and user logic. Also signals such as chip enable and other control signals can be modified by user logic before performing their function so that chips external to the FPGA can be eliminated. Upon power-up of the chip, each programmable switch connects its pad to the programming logic which programs configuration memory, so that the programming logic can receive instructions from an external source and control programming of the core logic of the chip. The configuration memory programs not only the internal circuitry accessed by the user but also the programmable switch itself. Thus as configuration proceeds, or after configuration is completed, the programmable switch can be reconfigured to connect internal portions of the FPGA user logic to parts of the configuration memory which were initially loaded from external pins.

Inventors

  • 👤 Thomas A. Kean

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 17:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17772; H03K19/17704; H03K19/17736; H03K19/17744; H03K19/17756; H03K19/1778; H03K19/17788

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 72 words
A programmable logic device comprising: a user logic structure; a configuration memory for controlling said user logic structure; structure for accessing said configuration memory; a plurality of pads for connecting external signals to said programmable logic device; a programmable switch, said programmable switch being programmable to connect signals between said pads, said user logic structure, and said structure for accessing said configuration memory, said programmable switch being programmed by said configuration memory.
Claim 2
Dependent Claim 72 words
A programmable logic device comprising: a user logic structure; a configuration memory for controlling said user logic structure; structure for accessing said configuration memory; a plurality of pads for connecting external signals to said programmable logic device; a programmable switch, said programmable switch being programmable to connect signals between said pads, said user logic structure, and said structure for accessing said configuration memory, said programmable switch being programmed by said configuration memory.
Claim 3
Dependent Claim 50 words
A programmable logic device as in claim 1 in which said programmable switch includes a multiplexer which receives as input signals a signal from one of said pads and a signal from said user logic structure and provides as output a signal to said structure for accessing said configuration memory.
Claim 4
Dependent Claim 51 words
A programmable logic device as in claim 1 in which said programmable switch includes a multiplexer which receives as input signals a signal from said user logic structure and a signal from said structure for accessing said configuration memory and provides as an output a signal to one of said pads.
Claim 5
Dependent Claim 43 words
A programmable logic device as in claim 3 in which said signal to one of said pads is programmably provided to said pad in response to an enable signal derived from said user logic structure and said structure for accessing said configuration memory.
Claim 6
Dependent Claim 35 words
A programmable logic device as in claim 3 in which said signal to one of said pads is programmably provided to said pad in response to an enable signal derived from said user logic structure.
Claim 7
Dependent Claim 47 words
A programmable logic device as in claim 1 in which said programmable switch includes a multiplexer which receives as input signals a signal from said user logic structure and a signal from one of said pads and provides as output a signal to said user logic structure.

References Cited (Backward Citations)

USRE34363E Cited
EP0253530A2 Cited
US5343406A Cited
US5084636A Cited
WO1992020157A1 Cited
US5237218A Cited
US5237219A Cited
WO1994001867A1 Cited
WO1994010754A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-01-05 2001-07-07 2002-01-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-01-05 2005-07-07 2006-01-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-01-05 2009-07-07 2010-01-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag