US4686691A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-purpose register for data and control paths having different path widths
Assignee: Unisys Corp
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Filing: 1984-12-04
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Granted: 1987-08-11
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Expires: 2004-12-04
Abstract
Abstract A multi-purpose register formed of various cells of a customized integrated circuit gate array chip having input gate cells, multiplexor cells, flip-flop cells and output gate cells. The flip-flop cells may be segmented into registers of different widths or may be employed as individual flip-flop cells depending upon the mode in which the register array is to be employed.
Inventors
- 👤 Gregory K. Deal
- 👤 Richard J. Manco
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:43
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C19/00; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
134 words
A register circuit comprising: a plurality of flip-flop circuits; a plurality of output circuits, one for each flip-flop circuit; a plurality of input circuits; switching means coupled between said input circuits and said flip-flop circuits to selectively form a parallel register of n bits in width where n can vary from one to the total number of said plurality of flip-flop circuits where each flip-flop circuit represents a particular significant bit; mode control means coupled to said switching means to indicate the number of flip-flop circuits to be connected to form said register; said switching means being multiplexor circuits coupled to said respective flip-flop circuits and to said input circuits; and each multiplexor circuit being selectively coupled to the output circuit of the next lowest significant bit flip-flop circuit to form a shift register.
Claim 2
Dependent Claim
134 words
A register circuit comprising: a plurality of flip-flop circuits; a plurality of output circuits, one for each flip-flop circuit; a plurality of input circuits; switching means coupled between said input circuits and said flip-flop circuits to selectively form a parallel register of n bits in width where n can vary from one to the total number of said plurality of flip-flop circuits where each flip-flop circuit represents a particular significant bit; mode control means coupled to said switching means to indicate the number of flip-flop circuits to be connected to form said register; said switching means being multiplexor circuits coupled to said respective flip-flop circuits and to said input circuits; and each multiplexor circuit being selectively coupled to the output circuit of the next lowest significant bit flip-flop circuit to form a shift register.
Claim 3
Dependent Claim
48 words
A register circuit according to claim 1 further including: mode control means coupled to said flip-flops to indicate the number of flip-flops to be connected to form said register, said mode control means being coupled to the next lowest significant bit flip-flop circuit to receive mode indicating signals.
Claim 4
Dependent Claim
134 words
An integrated circuit comprising: a plurality of flip-flop circuits; a plurality of output circuits, one for each flip-flop circuit; a plurality of input circuits; switching means coupled between said input circuits and said flip-flop circuits to selectively form a parallel register of n bits in width where n can vary from one to the total number of said plurality of flip-flop circuits where each flip-flop circuit represents a particular significant bit; mode control means coupled to said switching means to indicate the number of flip-flop circuits to be connected to form said register; said switching means being multiplexor circuits coupled to said respective flip-flop circuits and to said input circuits; and each multiplexor circuit being selectively coupled to the output circuit of the next lowest significant bit flip-flop circuit to form a shift register.
Claim 5
Dependent Claim
134 words
An integrated circuit comprising: a plurality of flip-flop circuits; a plurality of output circuits, one for each flip-flop circuit; a plurality of input circuits; switching means coupled between said input circuits and said flip-flop circuits to selectively form a parallel register of n bits in width where n can vary from one to the total number of said plurality of flip-flop circuits where each flip-flop circuit represents a particular significant bit; mode control means coupled to said switching means to indicate the number of flip-flop circuits to be connected to form said register; said switching means being multiplexor circuits coupled to said respective flip-flop circuits and to said input circuits; and each multiplexor circuit being selectively coupled to the output circuit of the next lowest significant bit flip-flop circuit to form a shift register.
Claim 6
Dependent Claim
30 words
An integrated circuit according to claim 3 wherein: mode control means coupled to said switching means to indicate the number of flip-flop circuits to be connected to form said register.
Claim 7
Dependent Claim
25 words
An integrated circuit according to claim 3 wherein: said switching means are multiplexor circuits coupled to said respective flip-flop circuits and to said input circuits.
Claim 8
Dependent Claim
48 words
An integrated circuit according to claim 3 further including: mode control means coupled to said flip-flops to indicate the number of flip-flops to be connected to form said register, said mode control means being coupled to the next lowest significant bit flip-flop circuit to receive mode indicating signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-10 | 1991-02-09 | 1991-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-10 | 1995-02-09 | 1995-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-10 | 1999-02-09 | 1999-08-11 | $7700.00 | Window Closed / Lapsed |