US3605024A
Expired / Lapsed
US
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Apparatus for shifting data in a long register
Assignee: Lockheed Martin Tactical Systems Inc
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Filing: 1970-06-01
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Granted: 1971-09-14
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Expires: 1990-06-01
Abstract
Abstract An improved shift register and interconnection of components related thereto is provided. With just two sets of connections between stages of a shift register of length 2n-1 where n is a positive integer, any end-around shift can be performed with n shift pulses. Modifications of the apparatus allow any register length with a slight loss in efficiency.
Inventors
- 👤 Kenneth E Batcher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:55
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/01; G06F5/015
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
486 words
Apparatus for shifting data in a register which comprises a plurality of shift register units greater than fourteen and less than some integral power of a positive integer which is relatively prime to the number of units, each unit having a storage device for storing data, three data inputs and means for selecting anyone of the three data inputs and setting the state of the storage device to the state of the selected input, means for selecting in common either the first data input of every unit, the second data input of every unit or the third data input of every unit so that the storage device of each unit can be set to the state of its selected input, interconnection means for transmitting the stored state of each shift register unit to the first data input of the same unit or another unit according to the following: for each positive integer, i, not greater than the number of units, the stored state of the ith unit is transmitted to the first data input of the jth unit where j is the positive integer not greater than the number of units such than j itself or the sum of j and the number of units or the sum of j and some multiple of the number of units equals the product of i and the aforementioned integer relatively prime to the number of units, interconnection means for transmitting the stored state of the ith unit to the second data input of the i+ 1th unit for each positive integer i less than the number of units and for transmitting the stored state of the last unit to the second data input of the first unit, and interconnection means for transmitting the stored sTate of each shift register unit to the third data input of the same unit or another unit according to the following: for each positive integer, i, not greater than the number of units the stored state of the ith unit is transmitted to the third data input of the jth unit where j is the positive integer not greater than the number of units such that j itself or the sum of j and the number of units or the sum of j and some multiple of the number of units equals the product of i and the aforementioned integer relatively prime to the number of units and the particular positive integer less than the number of units which particular integer when multiplied by the aforementioned integral power of the aforementioned integer relatively prime to the number of units yields a product which equals either the sum of one and the number of units or the sum of one and a multiple of the number of units, and means to coordinate the means for selecting with the interconnection means on a timing cycle to effect shifting of data among the shift register units.
Claim 2
Dependent Claim
486 words
Apparatus for shifting data in a register which comprises a plurality of shift register units greater than fourteen and less than some integral power of a positive integer which is relatively prime to the number of units, each unit having a storage device for storing data, three data inputs and means for selecting anyone of the three data inputs and setting the state of the storage device to the state of the selected input, means for selecting in common either the first data input of every unit, the second data input of every unit or the third data input of every unit so that the storage device of each unit can be set to the state of its selected input, interconnection means for transmitting the stored state of each shift register unit to the first data input of the same unit or another unit according to the following: for each positive integer, i, not greater than the number of units, the stored state of the ith unit is transmitted to the first data input of the jth unit where j is the positive integer not greater than the number of units such than j itself or the sum of j and the number of units or the sum of j and some multiple of the number of units equals the product of i and the aforementioned integer relatively prime to the number of units, interconnection means for transmitting the stored state of the ith unit to the second data input of the i+ 1th unit for each positive integer i less than the number of units and for transmitting the stored state of the last unit to the second data input of the first unit, and interconnection means for transmitting the stored sTate of each shift register unit to the third data input of the same unit or another unit according to the following: for each positive integer, i, not greater than the number of units the stored state of the ith unit is transmitted to the third data input of the jth unit where j is the positive integer not greater than the number of units such that j itself or the sum of j and the number of units or the sum of j and some multiple of the number of units equals the product of i and the aforementioned integer relatively prime to the number of units and the particular positive integer less than the number of units which particular integer when multiplied by the aforementioned integral power of the aforementioned integer relatively prime to the number of units yields a product which equals either the sum of one and the number of units or the sum of one and a multiple of the number of units, and means to coordinate the means for selecting with the interconnection means on a timing cycle to effect shifting of data among the shift register units.
Claim 3
Dependent Claim
33 words
If i is a positive integer greater than seven and less than 15 then the Q output of unit R(i) feeds the B-input of unit R(2i-15) and the A-input of unit R(2i-14); and
Claim 4
Dependent Claim
33 words
If i is a positive integer greater than seven and less than 15 then the Q output of unit R(i) feeds the B-input of unit R(2i-15) and the A-input of unit R(2i-14); and
Claim 5
Dependent Claim
304 words
Apparatus for shifting data in a register which comprises a plurality of shift register units greater than 14, where either the number of units or a multiple of the number of units equals an integral power of an integer less one, each unit having a storage device for storing a state, two data inputs and means for selecting either of the two data inputs and setting the state of the storage device to the state of the selected input, means for selecting in common either the first data input of every unit, or the second data input of every unit so that the storage device of each unit can be set to the state of its selected input, interconnection means for transmitting the stored state of each shift register unit to the first data input of the same unit or another unit according to the following: for each positive integer, i, not greater than the number of units the stored state of the ith unit is transmitted to the first data input of the jth unit where j is the positive integer not greater than the number of units such that j itself or the sum of j and the number of units or the sum of j and some multiple of the number of units equals the product of i and the aforementioned integer with an integral power equal to the sum of one and the number of units or the sum of one and a multiple of the number of units, and interconnection means for transmitting the stored state of the ith unit to the second data input of the i1th unit for each positive integer i less than the number of units and for transmitting the stored state of the last unit to the second data input of the first unit.
Claim 6
Dependent Claim
304 words
Apparatus for shifting data in a register which comprises a plurality of shift register units greater than 14, where either the number of units or a multiple of the number of units equals an integral power of an integer less one, each unit having a storage device for storing a state, two data inputs and means for selecting either of the two data inputs and setting the state of the storage device to the state of the selected input, means for selecting in common either the first data input of every unit, or the second data input of every unit so that the storage device of each unit can be set to the state of its selected input, interconnection means for transmitting the stored state of each shift register unit to the first data input of the same unit or another unit according to the following: for each positive integer, i, not greater than the number of units the stored state of the ith unit is transmitted to the first data input of the jth unit where j is the positive integer not greater than the number of units such that j itself or the sum of j and the number of units or the sum of j and some multiple of the number of units equals the product of i and the aforementioned integer with an integral power equal to the sum of one and the number of units or the sum of one and a multiple of the number of units, and interconnection means for transmitting the stored state of the ith unit to the second data input of the i1th unit for each positive integer i less than the number of units and for transmitting the stored state of the last unit to the second data input of the first unit.
Claim 7
Dependent Claim
258 words
The Q output of the last unit feeds the B-input of thE last unit and the A input of the first unit; a shift count register having stages C0 to C3 and having the same inputs and outputs as the units, means connecting the C-inputs of the shift count register to a clock count control input, means connecting the SA inputs of the shift count register to an enter count control input, means connecting the SB inputs of the shift count register to a shift count control input, means to enter four-bit binary numbers in a range equal to the number of units into the A-input of each stage of the shift count register, means connecting the Q output of stage C2 to the B-input of stage C3, means connecting the Q-output of stage C1 to the B-input of stage C2, means connecting the Q-output of stage C0 to the B-input of stage C1, and means feeding the B-input of stage C0 with a constant zero input, means connecting the Q-output of stage C3 to the SA input of all units, an inverter receiving the Q-output of stage C-3 and the SB input of all units, and means to control a clock cycle on the count register according to the following sequence a. initiate an enter count b. during the enter count initiate a count clock, c. shift the stages in the count register by initiating a shift count and a count clock during the same time period, and d. shifting the register by initiating the register clock.
Claim 8
Dependent Claim
258 words
The Q output of the last unit feeds the B-input of thE last unit and the A input of the first unit; a shift count register having stages C0 to C3 and having the same inputs and outputs as the units, means connecting the C-inputs of the shift count register to a clock count control input, means connecting the SA inputs of the shift count register to an enter count control input, means connecting the SB inputs of the shift count register to a shift count control input, means to enter four-bit binary numbers in a range equal to the number of units into the A-input of each stage of the shift count register, means connecting the Q output of stage C2 to the B-input of stage C3, means connecting the Q-output of stage C1 to the B-input of stage C2, means connecting the Q-output of stage C0 to the B-input of stage C1, and means feeding the B-input of stage C0 with a constant zero input, means connecting the Q-output of stage C3 to the SA input of all units, an inverter receiving the Q-output of stage C-3 and the SB input of all units, and means to control a clock cycle on the count register according to the following sequence a. initiate an enter count b. during the enter count initiate a count clock, c. shift the stages in the count register by initiating a shift count and a count clock during the same time period, and d. shifting the register by initiating the register clock.
Claim 9
Dependent Claim
421 words
Apparatus for shifting data in a register which comprises a plurality of shift register units greater than 14 and less than some integral power of a positive integer which is relatively prime to the number of units, each unit having a storage device for storing a state, a number of data inputs which number is the aforementioned integer and means for selecting anyone of the data inputs and setting the state of the storage device to the state of the selected input, means for selecting in common corresponding inputs of all units, interconnecting means for transmitting the stored state of each shift register unit to certain data inputs of certain units according to the following: for each positive integer, i, not greater than the number of units, and for each positive integer, k, not greater than the aforementioned integer which is relatively prime to the number of units, the stored state of the ith unit is transmitted to the kth data input of the jth unit where j is the positive integer not greater than the number of units such that j itself or the sum of j and The number of units or the sum of j and some multiple of the number of units equals the sum of two quantities one quantity is k minus one and the other quantity is the product of i and the aforementioned integer, and interconnecting means for transmitting the stored state of each shift register unit to the last data input of the same unit or another unit according to the following: for each positive integer, i, not greater than the number of units the stored state of the ith unit is transmitted to the last data input of the jth unit where j is the positive integer not greater than the number of units such that j itself or the sum of j and the number of units or the sum of j and some multiple of the number of units equals the product of i and the particular positive integer less than the number of units which particular integer when multiplied by the aforementioned integral power of the aforementioned integer relatively prime to the number of units yields a product which equals either the sum of one and the number of units or the sum of one and a multiple of the number of units, and means to coordinate the means for selecting with the interconnection means on a timing cycle to effect shifting of data among the shift register units.
Claim 10
Dependent Claim
421 words
Apparatus for shifting data in a register which comprises a plurality of shift register units greater than 14 and less than some integral power of a positive integer which is relatively prime to the number of units, each unit having a storage device for storing a state, a number of data inputs which number is the aforementioned integer and means for selecting anyone of the data inputs and setting the state of the storage device to the state of the selected input, means for selecting in common corresponding inputs of all units, interconnecting means for transmitting the stored state of each shift register unit to certain data inputs of certain units according to the following: for each positive integer, i, not greater than the number of units, and for each positive integer, k, not greater than the aforementioned integer which is relatively prime to the number of units, the stored state of the ith unit is transmitted to the kth data input of the jth unit where j is the positive integer not greater than the number of units such that j itself or the sum of j and The number of units or the sum of j and some multiple of the number of units equals the sum of two quantities one quantity is k minus one and the other quantity is the product of i and the aforementioned integer, and interconnecting means for transmitting the stored state of each shift register unit to the last data input of the same unit or another unit according to the following: for each positive integer, i, not greater than the number of units the stored state of the ith unit is transmitted to the last data input of the jth unit where j is the positive integer not greater than the number of units such that j itself or the sum of j and the number of units or the sum of j and some multiple of the number of units equals the product of i and the particular positive integer less than the number of units which particular integer when multiplied by the aforementioned integral power of the aforementioned integer relatively prime to the number of units yields a product which equals either the sum of one and the number of units or the sum of one and a multiple of the number of units, and means to coordinate the means for selecting with the interconnection means on a timing cycle to effect shifting of data among the shift register units.
Claim 11
Dependent Claim
291 words
Apparatus for shifting data in a register which comprises a plurality of shift register units greater than fourteen where either the number of units or a multiple of the number of units equals an integral power of an integer less one each unit having a storage device for storing a state, a number of data inputs which number is the aforementioned integer with an integral power equal to the sum of one and the number of units or the sum of one and a multiple of the number of units and means for selecting anyone of the data inputs and setting the state of the storage device to the state of the selected input, means for selecting in common corresponding inputs of all units, interconnecting means for transmitting the stored state of each shift register unit to certain data inputs of certain units according to the following: for each positive integer, i, not greater than the number of units and for each positive integer, k, not greater than the aforementioned integer which is relatively prime to the number of units, the stored state of the ith unit is transmitted to the kth data input of the jth unit where j is the positive integer not greater than the number of units such that j itself or the sum of j and the number of units or the sum of j and some multiple of the number of units equals the sum of two quantities one quantity is k minus one and the other quantity is the product of i and the aforementioned integer with an integral power equal to the sum of one and the number of units or the sum of one and a multiple of the number of units.
Claim 12
Dependent Claim
291 words
Apparatus for shifting data in a register which comprises a plurality of shift register units greater than fourteen where either the number of units or a multiple of the number of units equals an integral power of an integer less one each unit having a storage device for storing a state, a number of data inputs which number is the aforementioned integer with an integral power equal to the sum of one and the number of units or the sum of one and a multiple of the number of units and means for selecting anyone of the data inputs and setting the state of the storage device to the state of the selected input, means for selecting in common corresponding inputs of all units, interconnecting means for transmitting the stored state of each shift register unit to certain data inputs of certain units according to the following: for each positive integer, i, not greater than the number of units and for each positive integer, k, not greater than the aforementioned integer which is relatively prime to the number of units, the stored state of the ith unit is transmitted to the kth data input of the jth unit where j is the positive integer not greater than the number of units such that j itself or the sum of j and the number of units or the sum of j and some multiple of the number of units equals the sum of two quantities one quantity is k minus one and the other quantity is the product of i and the aforementioned integer with an integral power equal to the sum of one and the number of units or the sum of one and a multiple of the number of units.
Claim 13
Dependent Claim
88 words
Apparatus for shifting data in a long register which comprises a plurality of three input shift register units equal to the number of shift stages desired where such number is 15, each unit having at least an A, B and Q output, and a SA, C and SB input, means connecting a register clock control input common to the C input of each unit, means connecting the Q output of each unit to the A-input of one unit and the B-input of another unit according to the following:
Claim 14
Dependent Claim
88 words
Apparatus for shifting data in a long register which comprises a plurality of three input shift register units equal to the number of shift stages desired where such number is 15, each unit having at least an A, B and Q output, and a SA, C and SB input, means connecting a register clock control input common to the C input of each unit, means connecting the Q output of each unit to the A-input of one unit and the B-input of another unit according to the following:
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-13 | 1975-03-15 | 1975-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-13 | 1979-03-15 | 1979-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-13 | 1983-03-15 | 1983-09-14 | $7700.00 | Window Closed / Lapsed |