US4396829A
Expired / Lapsed
US
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Logic circuit
Assignee: Fujitsu Ltd
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Filing: 1980-11-07
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Granted: 1983-08-02
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Expires: 2000-11-07
Abstract
Abstract A logical circuit which is capable of serving not only as a shift register but also as counter, comprises a cascade-connection of flip-flops of the same number as the number of bits required. The flip-flops have an input connected to a logical gate group composed of gates which are opened and closed by a shift signal and a count signal. The logical circuit does not require that a flip-flop be included for each shift register part and counter part for each bit, but only requires one flip-flop to perform both the count and shift function. The logical circuit is capable of performing an independent operation of a shift register, an independent operation of a counter and a compound operation of inputting data in a serial fashion for initialization and outputting counted data in a serial fashion. With the logical circuit of the present invention, the number of gates used is greatly reduced as compared with the prior art shift register/counter circuit; accordingly, the circuit of the present invention is of particular utility when formed as a large scale integrated circuit.
Inventors
- 👤 Takanori Sugihara
- 👤 Makoto Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:09
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/54; G; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
215 words
A logical circuit, operatively connectable to receive a shift signal and a count signal, comprising: a plurality of cascade-connected flip-flops, each having an input; and logical gate groups, each having an output operatively connected to the input of the respective flip-flop, including gates to be opened and closed by the shift signal and the count signal so that the respective flip-flop serves as a shift register or a counter in response to the shift signal and the count signal; said logical circuit operatively connectable to receive serial input data Sin, and the nth logical gate group, operatively connected to the input of the nth (n=1, 2, 3, . . . ) flip-flop, have the construction represented by the following expression: D.sub.N =(SHT·Q.sub.(n-1))+(CRY·Q.sub.n)+(CNT·CRY.multidot.Q.sub.n) where D n is the input to the nth flip-flop and the output from the nth logical gate group, SHT is the shift signal, CNT is the count signal and bears a relationship to the shift signal SHT of CNT=SHT, Q n is the Q output of the nth flip-flop Q n is the Q output of the nth flip-flop, Q.sub.(n-) is the Q output of the (n-1)th flip-flop for n greater than 1, Q(n-1) is serial input data Sin when n=1, and CRY=Q 1 ·Q 2 ·Q 3 . . . ·Q.sub.(n-1).
Claim 2
Dependent Claim
215 words
A logical circuit, operatively connectable to receive a shift signal and a count signal, comprising: a plurality of cascade-connected flip-flops, each having an input; and logical gate groups, each having an output operatively connected to the input of the respective flip-flop, including gates to be opened and closed by the shift signal and the count signal so that the respective flip-flop serves as a shift register or a counter in response to the shift signal and the count signal; said logical circuit operatively connectable to receive serial input data Sin, and the nth logical gate group, operatively connected to the input of the nth (n=1, 2, 3, . . . ) flip-flop, have the construction represented by the following expression: D.sub.N =(SHT·Q.sub.(n-1))+(CRY·Q.sub.n)+(CNT·CRY.multidot.Q.sub.n) where D n is the input to the nth flip-flop and the output from the nth logical gate group, SHT is the shift signal, CNT is the count signal and bears a relationship to the shift signal SHT of CNT=SHT, Q n is the Q output of the nth flip-flop Q n is the Q output of the nth flip-flop, Q.sub.(n-) is the Q output of the (n-1)th flip-flop for n greater than 1, Q(n-1) is serial input data Sin when n=1, and CRY=Q 1 ·Q 2 ·Q 3 . . . ·Q.sub.(n-1).
Claim 3
Dependent Claim
30 words
A logical circuit, operatively connectable to receive serial input data and count data, comprising m shift counter means, where m is an integer greater than or equal to 3, including:
Claim 4
Dependent Claim
30 words
A logical circuit, operatively connectable to receive serial input data and count data, comprising m shift counter means, where m is an integer greater than or equal to 3, including:
Claim 5
Dependent Claim
345 words
means for receiving serial input data as initialization data; means for receiving count data and counting the count data; and means for transmitting serial output data which represents the initialization data as increased by the count data; each of said m shift counter means having an input and an output, the input of the first shift counter means operatively connectable to receive the serial input data and the count data, the output of the first shift counter means operatively connected to the input of the second shift counter means, the output of the (m-1)th shift counter means operatively connected to the input of the mth shift counter means, so that the output of the mth shift counter mans is a serial output of said logical circuit; said logical circuit operatively connectable to receive a shift signal, a count signal, a carry signal and a carry bar signal and each of said m shift counter means comprising: a flip-flop, having an input, having a flip-flop output for outputting a flip-flop output signal, and having a bar output for outputting a flip-flop bar output signal, wherein the flip-flop output is the output of said shift counter means; a first AND gate having a first input which is the input of said shift counter means and having a second input operatively connectable to receive the shift signal; a second AND gate having a first input, operatively connected to said flip-flop, for receiving the flip-flop output signal, having a second input operatively connectable to receive the carry bar signal; a third AND gate having a first input operatively connectable to receive the carry signal and having a second input operatively connected to said flip-flop, for receiving the flip-flop bar output signal; and an OR gate having a first input operatively connected to the output of said first AND gate, having a second input operatively connected to the output of said second AND gate, having a third input operatively connected to the output of said third AND gate, and having an output operatively connected to the input of said flip-flop.
Claim 6
Dependent Claim
345 words
means for receiving serial input data as initialization data; means for receiving count data and counting the count data; and means for transmitting serial output data which represents the initialization data as increased by the count data; each of said m shift counter means having an input and an output, the input of the first shift counter means operatively connectable to receive the serial input data and the count data, the output of the first shift counter means operatively connected to the input of the second shift counter means, the output of the (m-1)th shift counter means operatively connected to the input of the mth shift counter means, so that the output of the mth shift counter mans is a serial output of said logical circuit; said logical circuit operatively connectable to receive a shift signal, a count signal, a carry signal and a carry bar signal and each of said m shift counter means comprising: a flip-flop, having an input, having a flip-flop output for outputting a flip-flop output signal, and having a bar output for outputting a flip-flop bar output signal, wherein the flip-flop output is the output of said shift counter means; a first AND gate having a first input which is the input of said shift counter means and having a second input operatively connectable to receive the shift signal; a second AND gate having a first input, operatively connected to said flip-flop, for receiving the flip-flop output signal, having a second input operatively connectable to receive the carry bar signal; a third AND gate having a first input operatively connectable to receive the carry signal and having a second input operatively connected to said flip-flop, for receiving the flip-flop bar output signal; and an OR gate having a first input operatively connected to the output of said first AND gate, having a second input operatively connected to the output of said second AND gate, having a third input operatively connected to the output of said third AND gate, and having an output operatively connected to the input of said flip-flop.
Claim 7
Dependent Claim
79 words
A logical circuit according to claim 2, further comprising: a multiple input AND gate, having P inputs, where P is an integer greater than or equal to 2 and less than or equal to m, having a first input operatively connected to the output of said first shift counter means, and having the Pth input operatively connected to the output of the Pth shift counter means, so that the carry signal is generated by said multiple input AND gate.
Claim 8
Dependent Claim
19 words
A logical circuit according to claim 2, wherein the shift signal is the logical inverse of the count signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-01 | 1987-01-31 | 1987-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-01 | 1991-01-31 | 1991-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-01 | 1995-01-31 | 1995-08-02 | $7700.00 | Window Closed / Lapsed |