US3978413A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Modulus counter circuit utilizing serial access
Assignee: HP Inc
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Filing: 1975-02-07
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Granted: 1976-08-31
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Expires: 1995-02-07
Abstract
Abstract A circuit provides the dual functional capability of a modulus counter and a shift register, and does not require parallel access of the storage elements to preset or read the counter state.
Inventors
- 👤 Robert Alan Frohwerk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:14
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/502; H03K23/64; H03K23/66; H03K23/665
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
158 words
A circuit comprising: a shift register having a clock input, a data input and a data output and a plurality of memory elements; first circuit means coupled to the shift register for producing a feedback signal in response to selected states of the shift register; switching means having selectable count and shift states, and having inputs for receiving a shift signal, a count signal, a shift clock signal, and a state control signal, said switching means coupled to the first circuit means for receiving said feedback signal and coupled to the shift register for applying the shift signal to said data input and the shift clock signal to said clock input when said shift state is selected, and for applying the feedback signal to said data input and the count signal to said clock input when said count state is selected, said switching means selecting said count and shift states in response to only said state control signal.
Claim 2
Dependent Claim
158 words
A circuit comprising: a shift register having a clock input, a data input and a data output and a plurality of memory elements; first circuit means coupled to the shift register for producing a feedback signal in response to selected states of the shift register; switching means having selectable count and shift states, and having inputs for receiving a shift signal, a count signal, a shift clock signal, and a state control signal, said switching means coupled to the first circuit means for receiving said feedback signal and coupled to the shift register for applying the shift signal to said data input and the shift clock signal to said clock input when said shift state is selected, and for applying the feedback signal to said data input and the count signal to said clock input when said count state is selected, said switching means selecting said count and shift states in response to only said state control signal.
Claim 3
Dependent Claim
32 words
A circuit as in claim 1 further comprising a second circuit means coupled to said shift register for detecting a selected count state and for producing a carryout signal in response thereto.
Claim 4
Dependent Claim
43 words
A circuit as in claim 2 further comprising a gating means having an input for receiving a second control signal and being coupled to said shift register for coupling said data output to said data input in response to the second control signal.
Claim 5
Dependent Claim
63 words
A circuit as in claim 3, further comprising means for providing the shift clock signal at a frequency greater than the frequency of the count input signal by a factor which is larger than the number of memory elements in said shift register, whereby the contents of said shift register may be read out and restored between the recurrences of said count signal.
Claim 6
Dependent Claim
75 words
A circuit comprising a plurality of circuits as in claim 2, said plurality of circuits being concatenated one to the other, the carryout signal of each of said circuits being coupled to the count signal input of the next successive circuit, the shift signal being coupled to the shift signal input of the first of said circuits, wherein the carryout signal line of the last of said circuits comprises the sole user accessible data output.
Claim 7
Dependent Claim
36 words
The circuit of claim 5, further comprising gating means for coupling the carryout signal of the last of said circuits to the shift input of the first of said circuits in response to a restore-control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-31 | 1980-03-01 | 1980-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-31 | 1984-03-01 | 1984-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-31 | 1988-03-01 | 1988-08-31 | $7700.00 | Window Closed / Lapsed |