US3673390A
Expired / Lapsed
US
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Pulse counters
Assignee: Gemalto Terminals Ltd
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Filing: 1970-11-16
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Granted: 1972-06-27
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Expires: 1990-11-16
Abstract
Abstract A pulse counter has stages (such as decade stages) formed from binary circuits and preferably each based on a shift register. In the invention the binary circuits are reconnected in one large shift register whereby the digits can be shifted through the register to pass through one stage in turn, whereat they are read out in turn.
Inventors
- 👤 Peter Eric Krebs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:16
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/08
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
146 words
A multi-stage counter comprising a plurality p of cascaded stages, each stage being constructed to count one digit in a number system of radix n where n is greater than 2, each counter stage having a plurality m of binary circuits; circuit means for selectively interconnecting said plurality of stages as one of a multi-stage counter and a binary shift register, said circuit means including switch means for changing the configuration of said binary circuits from that composing the multi-stage counter to that of a binary shift register comprising the binary circuits and back, means for applying shift pulses to the stages in the shift register configuration and, in response to successive groups of m shift pulses, for shifting the counted digits through the said stages, and means for effecting dynamic readout of the digits as they are shifted one by one into said one stage.
Claim 2
Dependent Claim
146 words
A multi-stage counter comprising a plurality p of cascaded stages, each stage being constructed to count one digit in a number system of radix n where n is greater than 2, each counter stage having a plurality m of binary circuits; circuit means for selectively interconnecting said plurality of stages as one of a multi-stage counter and a binary shift register, said circuit means including switch means for changing the configuration of said binary circuits from that composing the multi-stage counter to that of a binary shift register comprising the binary circuits and back, means for applying shift pulses to the stages in the shift register configuration and, in response to successive groups of m shift pulses, for shifting the counted digits through the said stages, and means for effecting dynamic readout of the digits as they are shifted one by one into said one stage.
Claim 3
Dependent Claim
18 words
A multi-stage counter according to claim 1, comprising means for connecting said shift register as a recirculating register.
Claim 4
Dependent Claim
26 words
A multi-stage counter according to claim 1, wherein each counter stage is a decade stage consisting of a five-bit shift register connected in Johnson ring configuration.
Claim 5
Dependent Claim
34 words
A multi-stage counter according to claim 1, wherein the mEans for effecting dynamic readout comprise an n-line data highway and a decoder connected between the m circuits of said one stage and said highway.
Claim 6
Dependent Claim
39 words
A multi-stage counter according to claim 4, wherein the means for effecting dynamic readout includes means for switching the connectings between the m circuits of said one stage and the decoder to a complementary configuration to perform complementary decoding.
Claim 7
Dependent Claim
40 words
A multi-stage counter according to claim 1, further comprising position counter means for counting down the shift pulses by a factor of m and for energizing p position lines in succession in response to the successive groups of m pulses.
Claim 8
Dependent Claim
25 words
A multi-stage counter according to claim 6, wherein the position counter means comprises a p-stage ring counter and a divide-by-m circuit preceding the ring counter.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-27 | 1975-12-27 | 1976-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-27 | 1979-12-27 | 1980-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-27 | 1983-12-27 | 1984-06-27 | $7700.00 | Window Closed / Lapsed |