US3594765A
Expired / Lapsed
US
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Time division multiplex analog-digital or digital-analog converter
Assignee: International Standard Electric Corp
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Filing: 1968-12-26
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Granted: 1971-07-20
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Expires: 1988-12-26
Abstract
Abstract A plurality of binary counters are provided, each of which are assigned to a different channel signal, and arranged in two groups. A timing signal source and logic circuitry associated with each counter cooperate to cause the counters of one group to convert the analog or digital signal of that group and simultaneously connect the counters of the other group in series and to function as shift registers to produce the serial output of previously coded analog signals or to store serial digital input codes. The function of the counters are then reversed. When functioning as analog-digital converters, the counters start counting and the analog signals are compared to a reference sawtooth waveform. When the amplitude of the analog signal equals the amplitude of the waveform, the counting is stopped and the code stored therein represents the amplitude of the analog signal. In the digital-analog converter, the counters of a group which store digital codes previously shifted into these counters start counting and cooperate with a bistable device to produce PWM pulses which is operated on to reproduce the analog signals.
Inventors
- 👤 Claude Paul Henri Lerouge
- 👤 Marc Andre Regnier
- 👤 Didier Charles Strube
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:19
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
142 words
A converter comprising: a source of timing signals defining a first given time interval and a second given time interval different than said first time interval; binary counting means having an input and a plurality of outputs; a source of shift pulses coupled to the counting means and logic circuit means including an exclusive OR circuit coupled to said counting means and said source of timing signals, said logic circuit means responding to said timing signals to connect at least one of the outputs of said counting means to the input of said counting means to form a cyclic counter for one of said first and second time intervals and to disconnect the feedback from the said outputs to the said input and to connect said counting means as a shift register for the other of said first and second time intervals.
Claim 2
Dependent Claim
142 words
A converter comprising: a source of timing signals defining a first given time interval and a second given time interval different than said first time interval; binary counting means having an input and a plurality of outputs; a source of shift pulses coupled to the counting means and logic circuit means including an exclusive OR circuit coupled to said counting means and said source of timing signals, said logic circuit means responding to said timing signals to connect at least one of the outputs of said counting means to the input of said counting means to form a cyclic counter for one of said first and second time intervals and to disconnect the feedback from the said outputs to the said input and to connect said counting means as a shift register for the other of said first and second time intervals.
Claim 3
Dependent Claim
114 words
A converter according to claim 1, wherein said counting means includes a plurality of binary counters; and said logic circuit means includes a plurality of logic circuits, each of said logic circuits being coupled to a different one of said counters and in common to said source, each of said logic circuits responding to said timing sigNals to connect at least one of the outputs to the input of each of said counters to form separate cyclic counters for one of said first and second time intervals and to connect each of said counters as a shift register and in series with each other for the other of said first and second time intervals.
Claim 4
Dependent Claim
220 words
A converter according to claim 1, wherein said counting means includes a first group of a plurality of binary counters, and a second group of a plurality of binary counters; and said logic circuit means includes a first group of a plurality of logic circuits, each of said first group of logic circuits being coupled to a different one of said first group of counters and in common to said source, and a second group of a plurality of logic circuits, each of said second group of logic circuits being coupled to a different one of said second group of counters and in common to said source, each of said first group of logic circuits responding to said timing signals to connect each of said first group of counters as a cyclic counter for said first time interval and to connect each of said first group of counters as a shift register and in series with each other for said second time interval, and each of said second group of logic circuits responding to said timing signals to connect each of said second group of counters as a shift register and in series with each other for said first time interval and to connect each of said second group of counters as a cyclic counter for said second time interval.
Claim 5
Dependent Claim
41 words
A converter according to claim 3, wherein each of said counters of each of said first and second groups include n JK flip-flops, where n is an integer greater than one equal to the number of digits in a digital code.
Claim 6
Dependent Claim
173 words
A converter according to claim 3, further including a plurality of analog signal inputs, each of said inputs being associated with a different one of said counters of said first and second groups of said counters; a reference signal generator coupled to said source; a plurality of amplitude comparators, each of said comparators being coupled in common to said generator, a different one of said inputs and a different one of said logic circuits of said first and second groups to enable said first group of counters to code their associated analog signals during said first time interval and to enable said second group of counters to code their associated analog signals during said second time interval; and gate means coupled to said source and the last counter of each of said first and second groups of counters to provide as an output signal serial, digital codes from said second group of counters during said first time interval and serial, digital codes from said first group of counters during said second time interval.
Claim 7
Dependent Claim
29 words
A converter according to claim 5, further including a sync signal generator coupled to said source and said gate means to insert said sync signal into said output signal.
Claim 8
Dependent Claim
28 words
A converter according to claim 5, wherein said reference signal generator includes a sawtooth generator providing a sawtooth waveform during each of said first and second time intervals.
Claim 9
Dependent Claim
39 words
A converter according to claim 5, wherein each of said counters of said first and second groups include n JK flip-flops, where n is an integer greater than one equal to the number of digits in a digital code.
Claim 10
Dependent Claim
203 words
A converter according to claim 3, further including input means for serial digital codes coupled to the first logic circuit of each of said first and second groups of logic circuits to load each of said second group of counters with an associated digital code during said first time interval and to load each counter of said first group of counters with an associated digital code during said second time interval; a plurality of analog outputs, each of said outputs being associated with a different one of said counters of said first anD second groups of said counters; a plurality of decoders, each of said decoders being coupled to a different one of said counters of said first and second groups of said counters; and a plurality of bistable devices, each of said devices being coupled in common to said source and between a different one of said decoders and a different one of said outputs to provide an analog output signal on said outputs associated with each of said first group of counters during said first time interval and to provide an analog output signal on said outputs associated with each of said second group of counters during said second time interval.
Claim 11
Dependent Claim
21 words
A converter according to claim 9, wherein each of said devices includes a flip flop providing a pulse width modulated output.
References Cited (Backward Citations)
US2997233A
Cited
US3314015A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-19 | 1975-01-18 | 1975-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-19 | 1979-01-18 | 1979-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-19 | 1983-01-18 | 1983-07-20 | $7700.00 | Window Closed / Lapsed |