US6967514B2 — Method and apparatus for digital duty cycle adjus…

Claim 1

Independent Claim 164 words

A duty cycle adjuster comprising: a clock generator configured to generate a clock signal and having a duty cycle correction input; a duty cycle detector configured to generate an incremental error measurement in the presence of a duty cycle error in the clock signal, said duty cycle detector comprising a charge pump including a first and second capacitor and a switch in between said first and second capacitors, and an analog to digital converter configured to generate said incremental error measurement when a voltage difference across said first and second capacitors exceeds a threshold, and wherein said switch minimizes said voltage difference in response to a reset signal; a duty cycle error accumulator connected to said duty cycle detector, wherein said duty cycle error accumulator is configured to generate a duty cycle correction signal representing an accumulated error measurement in response to said incremental error measurement, said duty cycle error accumulator providing the duty cycle correction signal to is said duty cycle correction input.

Claim 2

Dependent Claim 164 words

A duty cycle adjuster comprising: a clock generator configured to generate a clock signal and having a duty cycle correction input; a duty cycle detector configured to generate an incremental error measurement in the presence of a duty cycle error in the clock signal, said duty cycle detector comprising a charge pump including a first and second capacitor and a switch in between said first and second capacitors, and an analog to digital converter configured to generate said incremental error measurement when a voltage difference across said first and second capacitors exceeds a threshold, and wherein said switch minimizes said voltage difference in response to a reset signal; a duty cycle error accumulator connected to said duty cycle detector, wherein said duty cycle error accumulator is configured to generate a duty cycle correction signal representing an accumulated error measurement in response to said incremental error measurement, said duty cycle error accumulator providing the duty cycle correction signal to is said duty cycle correction input.

Claim 3

Dependent Claim 53 words

The duty cycle adjuster of claim 1 , wherein the duty cycle adjuster is incorporated on a monolithic integrated circuit, wherein said clock signal has a rising edge and a falling edge and wherein said monolithic integrated circuit is adapted to transfer data on both rising and failing edges of the clock signal.

Claim 4

Dependent Claim 14 words

The duty cycle adjuster of claim 1 wherein said duty cycle detector is resettable.

Claim 5

Dependent Claim 28 words

The duty cycle adjuster of claim 3 , where said duty cycle adjuster is configured to reset the duty cycle detector after the incremental error measurement is generated.

Claim 6

Dependent Claim 51 words

The duty cycle adjuster of claim 1 wherein said incremental error measurement is in the form of a logic value, and wherein the logic value is selected from a first logic value which is indicative of a positive error and a second logic value which is indicative of a negative error.

Claim 7

Dependent Claim 14 words

The duty cycle adjuster of claim 1 wherein said duty cycle detector is programmable.

Claim 8

Dependent Claim 40 words

The duty cycle adjuster of claim 1 wherein said duty cycle detector comprises a charge pump and a digital to analog converter connected to said charge pump, said digital to analog converter having a digital input for duty cycle selection.

Claim 9

Dependent Claim 26 words

The duty cycle adjuster of claim 7 wherein said digital to analog converter is configured to adjust the charge and discharge rates of said charge pump.

Claim 10

Dependent Claim 18 words

The duty cycle adjuster of claim 7 wherein said digital to analog converter comprises a current steering circuit.

Claim 11

Dependent Claim 37 words

The duty cycle adjuster of claim 7 wherein said digital to analog converter comprises a plurality of capacitors, wherein said digital to analog converter is configured such that each of said capacitors is independently and selectively enabled.

Claim 12

Dependent Claim 17 words

The duty cycle adjuster of claim 1 wherein said duty cycle error accumulator comprises a digital counter.

Claim 13

Dependent Claim 16 words

The duty cycle adjuster of claim 11 wherein said digital counter has an adjustable counting increment.

Claim 14

Dependent Claim 22 words

The duty cycle adjuster of claim 12 wherein said counting increment is adjusted to increase the convergence of the duty cycle adjuster.

Claim 15

Dependent Claim 17 words

The duty cycle adjuster of claim 11 wherein said digital counter is settable to an initial value.

Claim 16

Dependent Claim 17 words

The duty cycle adjuster of claim 1 wherein said duty cycle error accumulator comprises a digital filter.

Claim 17

Dependent Claim 13 words

The duty cycle adjuster of claim 15 wherein said digital filter is nonlinear.

Claim 18

Dependent Claim 18 words

The duty cycle adjuster of claim 1 wherein said duty cycle error accumulator comprises a digital state machine.

Claim 19

Dependent Claim 16 words

The duty cycle adjuster of claim 17 wherein said digital state machine has a sleep state.

Claim 20

Dependent Claim 17 words

The duty cycle adjuster of claim 17 wherein said digital state machine has a fast lock state.

Claim 21

Dependent Claim 36 words

The duty cycle adjuster of claim 17 wherein said digital state machine is configured to increment said duty cycle correction signal by an amount responsive to the time in which said incremental error measurement is generated.

Claim 22

Dependent Claim 17 words

The duty cycle adjuster of claim 1 wherein said duty cycle correction signal is a digital signal.

Claim 23

Dependent Claim 29 words

The duty cycle adjuster of claim 1 wherein said duty cycle error accumulator comprises at least one capacitor, and wherein said duty cycle correction signal is an analog signal.

Claim 24

Dependent Claim 39 words

The duty cycle adjuster of claim 1 wherein said duty cycle detector generates a fine duty cycle adjustment signal, and wherein said duty cycle detector also provides the fine duty cycle correction signal to said duty cycle correction input.

Claim 25

Dependent Claim 200 words

A duty cycle adjuster comprising: a clock generator comprising a duty cycle shaping circuit and a clock waveform circuit, wherein said duty cycle shaping circuit comprises a first capacitor, a second capacitor, a differential amplifier connected to said first and second capacitors, and a digital to analog converter connected to said differential amplifier, and wherein the clock generator is configured to generate a clock signal and having a duty cycle correction input; a duty cycle detector configured to generate an incremental error measurement in the presence of a duty cycle error in the clock signal; a duty cycle error accumulator connected to said duty cycle detector, wherein said duty cycle error accumulator is configured to generate a duty cycle correction signal representing an accumulated error measurement in response to said incremental error measurement, said duty cycle error accumulator providing the duty cycle correction signal to said duty cycle correction input; and, wherein said digital to analog converter is configured to receive said duty cycle correction signal, responsively adjust current flow to at least one of said first and second capacitors, and to thereby adjust the rates of change of voltages on at least one of said first and second capacitors.

Claim 26

Dependent Claim 200 words

A duty cycle adjuster comprising: a clock generator comprising a duty cycle shaping circuit and a clock waveform circuit, wherein said duty cycle shaping circuit comprises a first capacitor, a second capacitor, a differential amplifier connected to said first and second capacitors, and a digital to analog converter connected to said differential amplifier, and wherein the clock generator is configured to generate a clock signal and having a duty cycle correction input; a duty cycle detector configured to generate an incremental error measurement in the presence of a duty cycle error in the clock signal; a duty cycle error accumulator connected to said duty cycle detector, wherein said duty cycle error accumulator is configured to generate a duty cycle correction signal representing an accumulated error measurement in response to said incremental error measurement, said duty cycle error accumulator providing the duty cycle correction signal to said duty cycle correction input; and, wherein said digital to analog converter is configured to receive said duty cycle correction signal, responsively adjust current flow to at least one of said first and second capacitors, and to thereby adjust the rates of change of voltages on at least one of said first and second capacitors.

Claim 27

Dependent Claim 91 words

The duty cycle adjuster of claim 24 wherein said duty cycle shaping circuit comprises a first capacitor, a second capacitor, a differential amplifier connected to said first and second capacitors, and a digital to analog converter connected to said differential amplifier, wherein said digital to analog converter is configured to receive said duty cycle correction signal, responsively adjust a capacitive value of at least one of said first and second capacitors, and to thereby adjust the rates of change of voltages on at least one of said first and second capacitors.

Claim 28

Dependent Claim 16 words

The duty cycle adjuster of claim 24 wherein said clock waveform circuit comprises an operational amplifier.

Claim 29

Dependent Claim 187 words

A duty cycle adjuster comprising: a clock generator configured to provide a clock signal and having a duty cycle correction input; a duty cycle detector comprising a charge pump including a first and second capacitor and a switch in between said first and second capacitors, configured to generate a voltage in the presence of a duty cycle error in the clock signal, and an analog to digital converter including a comparator connected to said charge pump, wherein said analog to digital converter is configured to generate a digital incremental error measurement responsive to said voltage; and a duty cycle error accumulator connected to said duty cycle detector, wherein said duty cycle error accumulator is configured to generate a duty cycle correction signal representing an accumulated error measurement in response to said digital incremental error measurement, said duty cycle error accumulator providing said duty cycle correction signal to said duty cycle correction input; wherein said charge pump is selectively resettable via said switch and configured to maintain said voltage substantially within a predetermined range when said duty cycle correction signal is sufficient to obtain a desired duty cycle.

Claim 30

Dependent Claim 187 words

A duty cycle adjuster comprising: a clock generator configured to provide a clock signal and having a duty cycle correction input; a duty cycle detector comprising a charge pump including a first and second capacitor and a switch in between said first and second capacitors, configured to generate a voltage in the presence of a duty cycle error in the clock signal, and an analog to digital converter including a comparator connected to said charge pump, wherein said analog to digital converter is configured to generate a digital incremental error measurement responsive to said voltage; and a duty cycle error accumulator connected to said duty cycle detector, wherein said duty cycle error accumulator is configured to generate a duty cycle correction signal representing an accumulated error measurement in response to said digital incremental error measurement, said duty cycle error accumulator providing said duty cycle correction signal to said duty cycle correction input; wherein said charge pump is selectively resettable via said switch and configured to maintain said voltage substantially within a predetermined range when said duty cycle correction signal is sufficient to obtain a desired duty cycle.

Claim 31

Dependent Claim 54 words

The duty cycle adjuster of claim 27 , wherein the duty cycle adjuster is integrated on a monolithic integrated circuit, wherein said clock signal has a rising edge and a falling edge and wherein said the monolithic integrated circuit is adapted to transfer data on both rising and falling edges of the clock signal.

Claim 32

Dependent Claim 26 words

The duty cycle adjuster of claim 27 wherein said digital incremental error measurement is a multiple bit signal representing a quantization value corresponding to said voltage.

Claim 33

Dependent Claim 52 words

The duty cycle adjuster of claim 27 wherein said digital incremental error measurement is in the form of a logic value, and wherein the logic value is selected from a first logic value which is indicative of a positive error and a second logic value which is indicative of a negative error.

Claim 34

Dependent Claim 26 words

The duty cycle adjuster of claim 30 wherein said switch is configured to reset said charge pump in response to said first and second logic values.

Claim 35

Dependent Claim 22 words

The duty cycle adjuster of claim 27 wherein said clock generator comprises a duty cycle shaping circuit and a clock waveform circuit.

Claim 36

Dependent Claim 89 words

The duty cycle adjuster of claim 32 wherein said duty cycle shaping circuit comprises a first capacitor, a second capacitor, a differential amplifier connected to said first and second capacitors, and a digital to analog converter connected to said differential amplifier, wherein said digital to analog converter is configured to receive said duty cycle correction signal, responsively adjust current flow to at least one of said first and second capacitors, and thereby adjust the rates of change of voltages on at least one of said first and second capacitors.

Claim 37

Dependent Claim 86 words

The duty cycle adjuster of claim 32 wherein said duty cycle shaping circuit comprises a first capacitor, a second capacitor, a differential amplifier connected to said first and second capacitors, and a digital to analog converter connected to said differential amplifier, wherein said digital to analog converter is configured to receive said duty cycle correction signal, responsively adjust a capacitive value of at least one of said first and second capacitors, and thereby adjust the rates of change of voltages on said first and second capacitors.

Claim 38

Dependent Claim 16 words

The duty cycle adjuster of claim 32 wherein said clock waveform circuit comprises an operational amplifier.

Claim 39

Dependent Claim 37 words

The duty cycle adjuster of claim 32 wherein said digital to analog converter comprises a plurality of capacitors, wherein said digital to analog converter is configured such that each of said capacitors is independently and selectively enabled.

Claim 40

Dependent Claim 14 words

The duty cycle adjuster of claim 27 wherein said duty cycle detector is programmable.

Claim 41

Dependent Claim 39 words

The duty cycle adjuster of claim 27 wherein said duty cycle detector further comprises a second digital to analog converter connected to said charge pump, said second digital to analog converter having a digital input for duty cycle selection.

Claim 42

Dependent Claim 27 words

The duty cycle adjuster of claim 38 wherein said second digital to analog converter is configured to adjust the charge and discharge rates of said charge pump.

Claim 43

Dependent Claim 19 words

The duty cycle adjuster of claim 38 wherein said second digital to analog converter comprises a current steering circuit.

Claim 44

Dependent Claim 17 words

The duty cycle adjuster of claim 27 wherein said duty cycle error accumulator comprises a digital counter.

Claim 45

Dependent Claim 16 words

The duty cycle adjuster of claim 41 wherein said digital counter has an adjustable counting increment.

Claim 46

Dependent Claim 17 words

The duty cycle adjuster of claim 41 wherein said digital counter is settable to an initial value.

Claim 47

Dependent Claim 17 words

The duty cycle adjuster of claim 27 wherein said duty cycle error accumulator comprises a digital filter.

Claim 48

Dependent Claim 13 words

The duty cycle adjuster of claim 44 wherein said digital filter is nonlinear.

Claim 49

Dependent Claim 18 words

The duty cycle adjuster of claim 27 wherein said duty cycle error accumulator comprises a digital state machine.

Claim 50

Dependent Claim 16 words

The duty cycle adjuster of claim 46 wherein said digital state machine has a sleep state.

Claim 51

Dependent Claim 17 words

The duty cycle adjuster of claim 46 wherein said digital state machine has a fast lock state.

Claim 52

Dependent Claim 36 words

The duty cycle adjuster of claim 46 wherein said digital state machine is configured to increment said duty cycle correction signal by an amount responsive to the speed at which said incremental error measurement is generated.

Claim 53

Independent Claim 110 words

A method of adjusting the duty cycle of a clock comprising the steps of: providing a clock signal to a charge pump having a first and second capacitor, and a switch connected between said first and second capacitor; generating an incremental error signal at a comparator having a threshold in response to the clock signal when a voltage difference across said first and second capacitors exceeds said threshold, and wherein said switch minimizes a voltage difference in response to a reset signal; generating a cumulative error signal in response to the incremental error signal; and adjusting the duty cycle of the clock signal in response to the cumulative error signal.

Claim 54

Independent Claim 110 words

A method of adjusting the duty cycle of a clock comprising the steps of: providing a clock signal to a charge pump having a first and second capacitor, and a switch connected between said first and second capacitor; generating an incremental error signal at a comparator having a threshold in response to the clock signal when a voltage difference across said first and second capacitors exceeds said threshold, and wherein said switch minimizes a voltage difference in response to a reset signal; generating a cumulative error signal in response to the incremental error signal; and adjusting the duty cycle of the clock signal in response to the cumulative error signal.

Claim 55

Dependent Claim 35 words

The method of claim 50 wherein the step of generating an incremental error signal comprises the step of: generating an incremental error signal having a logic value indicating whether the error is positive or negative.

Claim 56

Dependent Claim 23 words

The method of claim 51 wherein the step of generating an incremental duty cycle error voltage is performed by a programmable charge pump.

Claim 57

Dependent Claim 16 words

The method of claim 52 wherein the programmable charge pump includes a digital to analog converter.

Claim 58

Dependent Claim 44 words

The method of claim 50 wherein the step of generating an incremental error signal comprises the steps of: generating a voltage in response to the clock signal; and generating an incremental error signal having a digital quantization value representative of the differential voltage value.

Claim 59

Dependent Claim 25 words

The method of claim 54 further comprising the step of resetting the incremental error signal when the digital quantization value exceeds a digital threshold value.

Claim 60

Dependent Claim 27 words

The method of claim 50 wherein the step of generating a cumulative error signal in response to the incremental error signal comprises filtering the incremental error signal.

Claim 61

Dependent Claim 36 words

The method of claim 50 wherein the step of generating a cumulative error signal in response to the incremental error signal comprises altering a state of an error accumulator in response to the incremental error signal.

Claim 62

Dependent Claim 26 words

The method of claim 50 wherein the step of generating a cumulative error signal in response to the incremental error signal comprises adjusting a counter value.

Claim 63

Dependent Claim 22 words

The method of claim 58 wherein the counter value is incremented by a step size selected from a plurality of step sizes.

Claim 64

Dependent Claim 17 words

The method of claim 58 wherein the counter value is set according to a binary search algorithm.

Claim 65

Dependent Claim 30 words

The method of claim 50 wherein the step of adjusting the duty cycle of the clock signal in response to the cumulative error signal comprises adjusting a current steering circuit.

Claim 66

Dependent Claim 28 words

The method of claim 50 wherein the step of adjusting the duty cycle of the clock signal in response to the cumulative error signal comprises adjusting a capacitance.

Claim 67

Dependent Claim 29 words

The method of claim 50 wherein the step of adjusting the duty cycle of the clock signal in response to the cumulative error signal comprises adjusting a threshold voltage.

Claim 68

Dependent Claim 36 words

The method of claim 50 wherein the steps of generating an incremental error signal, generating a cumulative error signal, resetting the incremental error signal, and adjusting the duty cycle of the clock signal are repeatedly performed.

Claim 69

Dependent Claim 35 words

The method of claim 50 further comprising the steps of: generating a fine duty cycle adjustment signal; and adjusting the duty cycle of the clock signal in response to the fine duty cycle adjustment signal.

Claim 70

Dependent Claim 149 words

A duty cycle adjuster comprising: a clock generator configured to generate a clock signal and having a duty cycle correction input; a duty cycle detector configured to generate an incremental error measurement in response to an incremental error voltage exceeding a threshold, wherein the duty cycle detector generates a fine duty cycle correction signal, said duty cycle detector providing the fine duty cycle correction signal to said duty cycle correction input; and a duty cycle error accumulator connected to said duty cycle detector; wherein said duty cycle error accumulator is configured to generate a duty cycle correction signal representing an accumulated error measurement in response to said incremental error measurement, said duty cycle error accumulator providing the duty cycle correction signal to said duty cycle correction input; wherein the duty cycle detector is configured to reset the incremental error voltage when the incremental error measurement reaches a threshold value.

Claim 71

Dependent Claim 149 words

A duty cycle adjuster comprising: a clock generator configured to generate a clock signal and having a duty cycle correction input; a duty cycle detector configured to generate an incremental error measurement in response to an incremental error voltage exceeding a threshold, wherein the duty cycle detector generates a fine duty cycle correction signal, said duty cycle detector providing the fine duty cycle correction signal to said duty cycle correction input; and a duty cycle error accumulator connected to said duty cycle detector; wherein said duty cycle error accumulator is configured to generate a duty cycle correction signal representing an accumulated error measurement in response to said incremental error measurement, said duty cycle error accumulator providing the duty cycle correction signal to said duty cycle correction input; wherein the duty cycle detector is configured to reset the incremental error voltage when the incremental error measurement reaches a threshold value.

Claim 72

Dependent Claim 18 words

The duty cycle adjuster of claim 66 wherein the fine duty cycle correction signal is an analog voltage.

Claim 73

Dependent Claim 18 words

The duty cycle adjuster of claim 66 wherein the fine duty cycle correction signal is a digital signal.

Claim 74

Dependent Claim 17 words

The duty cycle adjuster of claim 68 wherein the duty cycle correction signal is a digital signal.

Claim 75

Dependent Claim 38 words

The duty cycle adjuster of claim 69 wherein the clock generator comprises a digital-to-analog converter having said duty cycle correction input, and said duty cycle correction signal and said fine duty cycle correction signal control said digital-to-analog converter.

Claim 76

Dependent Claim 38 words

The duty cycle adjuster of claim 66 wherein the clock generator comprises a first current steering circuit for receiving said duty cycle correction signal and a second current steering circuit for receiving said fine duty cycle correction signal.

Claim 77

Dependent Claim 19 words

The duty cycle adjuster of claim 71 wherein the first and second current steering circuits are both analog amplifiers.

Claim 78

Dependent Claim 27 words

The duty cycle adjuster of claim 71 wherein the first current steering circuit is a digital-to-analog converter, and said second current steering circuit is an analog amplifier.

Claim 79

Independent Claim 72 words

A method of adjusting the duty cycle of a clock comprising the steps of: providing a clock signal; generating an incremental error signal in response to the clock signal; generating a cumulative error signal in response to the incremental error signal; generating a fine adjustment signal in response to the clock signal; adjusting the duty cycle of the clock signal in response to the cumulative error signal and the fine adjustment signal.

Claim 80

Independent Claim 72 words

A method of adjusting the duty cycle of a clock comprising the steps of: providing a clock signal; generating an incremental error signal in response to the clock signal; generating a cumulative error signal in response to the incremental error signal; generating a fine adjustment signal in response to the clock signal; adjusting the duty cycle of the clock signal in response to the cumulative error signal and the fine adjustment signal.

Claim 81

Dependent Claim 56 words

The method of claim 74 wherein the step of generating an incremental error signal comprises: generating an error voltage in response to the clock signal; generating an incremental error signal when the error voltage exceeds a threshold; and, resetting the error voltage; and wherein the fine adjustment signal is generated in response to the error voltage.

Claim 82

Dependent Claim 57 words

The method of claim 74 wherein the step of adjusting the duty cycle of the clock signal in response to the cumulative error signal and the fine adjustment signal comprises: adjusting a first current steering circuit in response to the cumulative error signal; and, adjusting a second current steering circuit in response to the fine adjustment signal.

Claim 83

Dependent Claim 21 words

The method of claim 76 wherein at least one of the first and second current steering circuits is a digital-to-analog converter.

Claim 84

Dependent Claim 21 words

The method of claim 76 wherein at least one of the first and second current steering circuits is an analog amplifier.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2008-11-21	2009-05-23	2009-11-22	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2012-11-21	2013-05-23	2013-11-22	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2016-11-21	2017-05-23	2017-11-22	$7700.00	Window Closed / Lapsed

Method and apparatus for digital duty cycle adjustment

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