US6448828B2
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Apparatus and method for edge based duty cycle conversion
Assignee: Rambus Inc
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Filing: 2001-10-15
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Granted: 2002-09-10
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Expires: 2021-10-15
Abstract
Abstract A duty cycle converter generating a pair of output signals whose cross-point duty cycle is substantially equal to the edge duty cycle of a pair of input signals. The duty cycle converter includes an edge detector and a signal generator. The edge detector detects and indicates a first transition of a first input signal and a second transition of a second input signal. The signal generator takes the outputs of the edge detector and generates a first output signal and a second output signal. The signal generator causes the cross-point duty cycle of the first output signal to substantially equal the edge duty cycle of the first input cycle. The signal generator does so by forcing a first time delay between adjacent crossover points of the first and second output signals to be substantially equal to a second time delay between the first transition and the second transition.
Inventors
- 👤 Donald C. Stark
- 👤 Stefanos Sidiropoulos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:54
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534; H03K5/15; H03K5/151
Claims Analysis
Total Claims: 53
Claim 1
Independent Claim
150 words
An apparatus for duty cycle conversion comprising: an edge detector to detect a first transition of a first input signal and a second transition of a second input signal, the first and second input signals having an associated edge duty cycle, the first transition having a same polarity as the second transition; and a signal generator, coupled to the edge detector, to generate a first output signal and a second output signal offset from the first output signal, the first and second output signals having an associated cross-point duty cycle, the signal generator forcing a first time delay between adjacent cross-over points of the first and second output signals to substantially equal a second time delay between the first transition and the second transition, wherein the cross-point duty cycle of the first and second output signals is dependent upon the edge duty cycle of the first and second input signals.
Claim 2
Independent Claim
150 words
An apparatus for duty cycle conversion comprising: an edge detector to detect a first transition of a first input signal and a second transition of a second input signal, the first and second input signals having an associated edge duty cycle, the first transition having a same polarity as the second transition; and a signal generator, coupled to the edge detector, to generate a first output signal and a second output signal offset from the first output signal, the first and second output signals having an associated cross-point duty cycle, the signal generator forcing a first time delay between adjacent cross-over points of the first and second output signals to substantially equal a second time delay between the first transition and the second transition, wherein the cross-point duty cycle of the first and second output signals is dependent upon the edge duty cycle of the first and second input signals.
Claim 3
Dependent Claim
15 words
The apparatus of claim 1 wherein the first and second input signals are complementary signals.
Claim 4
Dependent Claim
16 words
The apparatus of claim 1 wherein the first and second input signals are complementary clock signals.
Claim 5
Dependent Claim
23 words
The apparatus of claim 3 wherein the edge detector is responsive to positive transitions of the first input signal and second input signal.
Claim 6
Dependent Claim
20 words
The apparatus of claim 4 wherein the edge detector detects the first and second transitions using a threshold voltage level.
Claim 7
Dependent Claim
18 words
The apparatus of claim 5 wherein the threshold voltage level is a midpoint of the first input signal.
Claim 8
Dependent Claim
18 words
The apparatus of claim 1 wherein the edge detector comprises a first and a second edge detector circuit.
Claim 9
Dependent Claim
52 words
The apparatus of claim 7 wherein the first edge detector comprises: inverter circuitry having an input and an output, the input receiving the first input signal; and a NAND gate having a first input to receive the first input signal and a second input coupled to the output of the inverter circuitry.
Claim 10
Dependent Claim
17 words
The apparatus of claim 8 wherein the inverter circuitry comprises an odd number of serially coupled inverters.
Claim 11
Dependent Claim
13 words
The apparatus of claim 1 wherein the signal generator comprises a Set-Reset flip-flop.
Claim 12
Dependent Claim
169 words
An edge duty cycle to cross-point duty cycle converter comprising: a first edge detector detecting a first transition of a first input signal, the first input signal having a first duty cycle; a second edge detector detecting a second transition of a second input signal, the second transition having a same polarity as the first transition; the first and second input signals having an associated edge duty cycle; and a signal generator coupled to the first and second edge detectors to generate a first output signal and a second output signal offset from the first output signal, the first and second output signals having an associated cross-point duty cycle, the signal generator forcing a first time delay between adjacent cross-over points of the first and second output signals to substantially equal a second time delay between the first transition and the second transition, wherein the cross-point duty cycle of the first and second output signals is dependent upon the edge duty cycle of the first and second input signals.
Claim 13
Dependent Claim
169 words
An edge duty cycle to cross-point duty cycle converter comprising: a first edge detector detecting a first transition of a first input signal, the first input signal having a first duty cycle; a second edge detector detecting a second transition of a second input signal, the second transition having a same polarity as the first transition; the first and second input signals having an associated edge duty cycle; and a signal generator coupled to the first and second edge detectors to generate a first output signal and a second output signal offset from the first output signal, the first and second output signals having an associated cross-point duty cycle, the signal generator forcing a first time delay between adjacent cross-over points of the first and second output signals to substantially equal a second time delay between the first transition and the second transition, wherein the cross-point duty cycle of the first and second output signals is dependent upon the edge duty cycle of the first and second input signals.
Claim 14
Dependent Claim
21 words
The edge duty cycle to cross-point duty cycle converter of claim 11 the first and second input signals are complementary signals.
Claim 15
Dependent Claim
23 words
The edge duty cycle to cross-point duty cycle converter of claim 11 wherein the first and second input signals are complementary clock signals.
Claim 16
Dependent Claim
71 words
The edge duty cycle to cross-point duty cycle converter of claim 11 wherein the first edge detector comprises: a first inverter circuit having a first inverter input and a first inverter output, the first inverter input receiving the first input signal; and a first NAND gate having a first NAND input to receive the first input signal and a second NAND input coupled to the output of the first inverter circuit.
Claim 17
Dependent Claim
70 words
The edge duty cycle to cross-point duty cycle converter of claim 14 wherein the second edge detector comprises: a second inverter circuit having a second inverter input and a second inverter output, the second inverter input receiving the second input signal; a second NAND gate having a third NAND input to receive the second input signal and a fourth NAND input coupled to the output of the second inverter circuit.
Claim 18
Dependent Claim
21 words
The edge to cross-point duty cycle converter of claim 15 wherein the first inverter circuit comprises an odd number of inverters.
Claim 19
Dependent Claim
21 words
The edge to cross-point duty cycle converter of claim 15 wherein the second inverter circuit comprises an odd number of inverters.
Claim 20
Dependent Claim
18 words
The edge to cross-point duty cycle converter of claim 14 wherein the signal generator comprises a Set-Reset flip-flop.
Claim 21
Dependent Claim
19 words
The edge to cross-point duty cycle converter of claim 11 wherein the polarity of the first transition is positive.
Claim 22
Dependent Claim
51 words
The edge duty cycle to cross-point duty cycle converter of claim 11 wherein the first edge detector detects the first transition using a first threshold voltage level and wherein the second edge detector detects the second transition using a second threshold voltage level substantially equal to the first threshold voltage level.
Claim 23
Dependent Claim
70 words
The edge duty cycle to cross-point duty cycle converter of claim 11 wherein the first edge detector comprises: a third inverter circuit having a third inverter input and a third inverter output, the third inverter input receiving the first input signal; a first NOR gate having a first NOR input to receive the first input signal and a second NOR input coupled to the output of the third inverter circuit.
Claim 24
Dependent Claim
70 words
The edge duty cycle to cross-point duty cycle converter of claim 21 wherein the second edge detector comprises: a fourth inverter circuit having a fourth inverter input and a fourth inverter output, the fourth inverter input receiving the second input signal; a second NOR gate having a third NOR input to receive the second input signal and a fourth NOR input coupled to the output of the fourth inverter circuit.
Claim 25
Dependent Claim
23 words
The edge duty cycle to cross-point duty cycle converter of claim 22 wherein the third inverter circuit comprises an odd number of inverters.
Claim 26
Dependent Claim
23 words
The edge duty cycle to cross-point duty cycle converter of claim 22 wherein the fourth inverter circuit comprises an odd number of inverters.
Claim 27
Dependent Claim
20 words
The edge duty cycle to cross-point duty cycle converter of claim 21 wherein the signal generator comprises a Set-Reset flip-flop.
Claim 28
Independent Claim
164 words
An apparatus comprising: a clock generator to generate first and second complementary clock signals having an associated edge duty cycle; a duty cycle converter, coupled to the clock generator, to convert the first and second clock signals into third and fourth complementary clock signals having an associated cross-point duty cycle, the duty cycle converter configured to force a first time delay between adjacent cross-over points of the third and fourth clock signals to substantially equal a second time delay between successive same polarity transitions of the first and second clock signals; and duty cycle correction circuitry, coupled between the duty cycle converter and the clock generator, to generate a clock control signal for input to the clock generator in response to the cross-point duty cycle of the third and fourth clock signals, the duty cycle correction circuitry adjusting the clock control signal so as to force same polarity edges of the first and second complementary clock signals to be separated by a predefined phase.
Claim 29
Independent Claim
164 words
An apparatus comprising: a clock generator to generate first and second complementary clock signals having an associated edge duty cycle; a duty cycle converter, coupled to the clock generator, to convert the first and second clock signals into third and fourth complementary clock signals having an associated cross-point duty cycle, the duty cycle converter configured to force a first time delay between adjacent cross-over points of the third and fourth clock signals to substantially equal a second time delay between successive same polarity transitions of the first and second clock signals; and duty cycle correction circuitry, coupled between the duty cycle converter and the clock generator, to generate a clock control signal for input to the clock generator in response to the cross-point duty cycle of the third and fourth clock signals, the duty cycle correction circuitry adjusting the clock control signal so as to force same polarity edges of the first and second complementary clock signals to be separated by a predefined phase.
Claim 30
Dependent Claim
16 words
The apparatus of claim 26 , wherein the clock control cycle is a fifth clock signal.
Claim 31
Dependent Claim
13 words
The apparatus of claim 26 , wherein the predefined phase is 180 degrees.
Claim 32
Dependent Claim
42 words
The apparatus of claim 26 , further including a circuit block, coupled to the clock generator to receive the first and second complementary clock signals, the circuit block utilizing the first and second complementary clock signals to perform a data communication task.
Claim 33
Dependent Claim
30 words
The apparatus of claim 29 , wherein the circuit block includes a data receiver that uses the first and second complementary clock signals to control receipt of a data signal.
Claim 34
Dependent Claim
131 words
The apparatus of claim 26 , wherein the duty cycle converter includes: an edge detector to detect a first transition of the first clock signal and a second transition of the second clock signal, the first transition having a same polarity as the second transition; and a signal generator, coupled to the edge detector, to generate the third clock signal and the clock fourth signal, offset from the third clock signal, the signal generator forcing a first time delay between adjacent cross-over points of the third and fourth clock signals to substantially equal a second time delay between the first transition and the second transition, wherein the cross-point duty cycle of the third and fourth clock signals is dependent upon the edge duty cycle of the first and second clock signals.
Claim 35
Dependent Claim
20 words
The apparatus of claim 31 wherein the edge detector detects the first and second transitions using a threshold voltage level.
Claim 36
Dependent Claim
18 words
The apparatus of claim 32 wherein the threshold voltage level is a midpoint of the first clock signal.
Claim 37
Dependent Claim
65 words
The apparatus of claim 31 wherein the edge detector comprises a first and a second edge detector circuit, and the first edge detector comprises: inverter circuitry having an input and an output, the input receiving the first clock signal; and a NAND gate having a first input to receive the first clock signal and a second input coupled to the output of the inverter circuitry.
Claim 38
Dependent Claim
17 words
The apparatus of claim 34 wherein the inverter circuitry comprises an odd number of serially coupled inverters.
Claim 39
Dependent Claim
13 words
The apparatus of claim 31 wherein the signal generator comprises a Set-Reset flip-flop.
Claim 40
Dependent Claim
143 words
A duty cycle conversion method comprising: detecting a first transition of a first input signal and a second transition of a second input signal, the first and second input signals having an associated edge duty cycle, the first transition having a same polarity as the second transition; and in response to detecting the first and second transitions, generating a first output signal and a second output signal offset from the first output signal, the first and second output signals having an associated cross-point duty cycle, including forcing a first time delay between adjacent cross-over points of the first and second output signals to substantially equal a second time delay between the first transition and the second transition, wherein the cross-point duty cycle of the first and second output signals is dependent upon the edge duty cycle of the first and second input signals.
Claim 41
Dependent Claim
143 words
A duty cycle conversion method comprising: detecting a first transition of a first input signal and a second transition of a second input signal, the first and second input signals having an associated edge duty cycle, the first transition having a same polarity as the second transition; and in response to detecting the first and second transitions, generating a first output signal and a second output signal offset from the first output signal, the first and second output signals having an associated cross-point duty cycle, including forcing a first time delay between adjacent cross-over points of the first and second output signals to substantially equal a second time delay between the first transition and the second transition, wherein the cross-point duty cycle of the first and second output signals is dependent upon the edge duty cycle of the first and second input signals.
Claim 42
Dependent Claim
21 words
The method of claim 37 wherein detecting the first transition comprises detecting a threshold voltage level of the first input signal.
Claim 43
Dependent Claim
18 words
The method of claim 38 wherein the threshold voltage level is a midpoint of the first input signal.
Claim 44
Dependent Claim
18 words
The method of claim 39 wherein the polarity of the first transition and the second transition is positive.
Claim 45
Dependent Claim
15 words
The method of claim 37 wherein the first and second input signals are complementary signals.
Claim 46
Dependent Claim
16 words
The method of claim 37 wherein the first and second input signals are complementary clock signals.
Claim 47
Dependent Claim
133 words
A signal generation method comprising: generating first and second complementary clock signals having an associated edge duty cycle; converting the first and second clock signals into third and fourth complementary clock signals having an associated cross-point duty cycle, including forcing a first time delay between adjacent cross-over points of the third and fourth clock signals to substantially equal a second time delay between successive same polarity transitions of the first and second clock signals; and generating a clock control signal, for controlling generation of the first and second complementary clock signals, in response to the cross-point duty cycle of the third and fourth clock signals, including adjusting the clock control signal so as to force same polarity edges of the first and second complementary clock signals to be separated by a predefined phase.
Claim 48
Dependent Claim
133 words
A signal generation method comprising: generating first and second complementary clock signals having an associated edge duty cycle; converting the first and second clock signals into third and fourth complementary clock signals having an associated cross-point duty cycle, including forcing a first time delay between adjacent cross-over points of the third and fourth clock signals to substantially equal a second time delay between successive same polarity transitions of the first and second clock signals; and generating a clock control signal, for controlling generation of the first and second complementary clock signals, in response to the cross-point duty cycle of the third and fourth clock signals, including adjusting the clock control signal so as to force same polarity edges of the first and second complementary clock signals to be separated by a predefined phase.
Claim 49
Dependent Claim
16 words
The method of claim 43 , wherein the clock control signal is a fifth clock signal.
Claim 50
Dependent Claim
13 words
The method of claim 43 , wherein the predefined phase is 180 degrees.
Claim 51
Dependent Claim
22 words
The method of claim 43 , further including utilizing the first and second complementary clock signals to perform a data communication task.
Claim 52
Dependent Claim
23 words
The method of claim 43 , further including utilizing the first and second complementary clock signals to control receipt of a data signal.
Claim 53
Dependent Claim
114 words
The method of claim 43 , wherein the converting includes: detecting a first transition of the first clock signal and a second transition of the second clock signal, the first transition having a same polarity as the second transition; and generating the third clock signal and the fourth clock signal, offset from the third clock signal, including forcing a first time delay between adjacent cross-over points of the third and fourth clock signals to substantially equal a second time delay between the first transition and the second transition, wherein the cross-point duty cycle of the third and fourth clock signals is dependent upon the edge duty cycle of the first and second clock signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-09 | 2006-03-11 | 2006-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-09 | 2010-03-11 | 2010-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-09 | 2014-03-11 | 2014-09-10 | $7700.00 | Window Closed / Lapsed |