Multiple clock source generation with independently adjustable duty cycles

Claim 2

A multiple phase clock generator comprising: (a) delay line means, coupled to receive an input clock having leading and trailing edges, for generating at least two clock signals delayed a predetermined time from the input clock; (b) edge detector means, coupled to the delay line means, for generating a pulse responsive to a predetermined edge on the at least two clock signals; and, (c) S-R means, coupled to the edge detector means, for generating at least two clock signals having a temporally common first edge and an independently adjustable second edge.

Claim 3

A multiple phase clock generator as recited in claim 1 wherein one of the at least two clock signals have a frequency ƒ and at least one of the at least two clock signals has a frequency which is an integer multiple of ƒ.

Claim 4

A multiple phase clock generator comprising: (a) first, second, and third delay lines, each having an input coupled to receive an input clock and an output; (b) first and second latches, each having a set input, a reset input, an output, and a complementary output; (c) a first edge detector coupled between the output of the first delay line and the set inputs on the first and second latches; (d) a second edge detector coupled between the output of the second delay line and the reset input on the first latch; and, (e) a third edge detector coupled between the output of the third delay line and the reset input on the second latch.

Claim 5

A multiple phase clock generator comprising: (a) first, second, and third delay lines, each having an input coupled to receive an input clock and an output; (b) first and second latches, each having a set input, a reset input, an output, and a complementary output; (c) a first edge detector coupled between the output of the first delay line and the set inputs on the first and second latches; (d) a second edge detector coupled between the output of the second delay line and the reset input on the first latch; and, (e) a third edge detector coupled between the output of the third delay line and the reset input on the second latch.

Claim 6

A multiple phase clock generator as recited in claim 3 further comprising third and fourth latches having set and reset inputs cross coupled with respect to the set and reset inputs of the first and second latches in (b), respectively.

Claim 7

A multiple phase clock generator as recited in claim 3 wherein the first delay line has a fixed delay of Δ1.

Claim 8

A multiple phase clock generator as recited in claim 3 wherein the second delay line has a programmable delay of Δ2.

Claim 9

A multiple phase clock generator as recited in claim 3 wherein the third delay line has a programmable delay of Δ3.

Claim 10

A multiple phase clock generator as recited in claim 3 wherein the first edge detector (c) detects rising edges.

Claim 11

A multiple phase clock generator as recited in claim 3 wherein the second edge detector (d) detects falling edges.

Claim 12

A multiple phase clock generator as recited in claim 3 wherein the third edge detector (e) detects falling edges.

Claim 13

A multiple phase clock generator as recited in claim 3 further comprising: (f) a NOR gate having a first input coupled to the first delay line output, a second input coupled to the second delay line output, and an output; (g) a third latch having a clock input coupled to the NOR gate output, a D input coupled to the complementary output of the second latch, and an output, and a complementary output; (h) a first AND gate having a first input coupled to the first edge detector, a second input coupled to the output of the third latch, and an output coupled to the set input on the second latch; and, (i) a second AND gate having a first input coupled to the third edge detector, a second input coupled to the complementary output of the third latch, and an output coupled to the reset input on the second latch.

Claim 14

An adjustable duty cycle clock generator as recited in claim 11 further comprising fourth and fifth latches having set and reset inputs cross coupled with respect to the set and reset inputs of the first and second latches in (b), respectively.

Claim 15

A computer system comprising: (a) at least two functional units; and, (b) clock generation means for generating at least two clock signals each having a common synchronous edge and an independently adjustable edge to clock the at least two functional units wherein data signals between the at least two functional units are transmitted on the common synchronous edges of the at least two clock signals.

Claim 16

A computer system comprising: (a) at least two functional units; and, (b) clock generation means for generating at least two clock signals each having a common synchronous edge and an independently adjustable edge to clock the at least two functional units wherein data signals between the at least two functional units are transmitted on the common synchronous edges of the at least two clock signals.

Claim 19

A computer system comprising: (a) a motherboard; (b) a processor disposed on the motherboard; (c) memory disposed on the motherboard and coupled to the processor; and, (d) a multiple phase clock generator including, (i) delay line means, coupled to receive an input clock, for generating at least two clock signals delayed a predetermined time from the input clock; (ii) edge detector means, coupled to the delay line means for generating a pulse responsive to a predetermined edge on the at least two clock signals; and, (iii) S-R means, coupled to the edge detector means, for generating at least two clock signals having a common edge and an independently adjustable second edge.

Claim 20

A computer system comprising: (a) a motherboard; (b) a processor disposed on the motherboard; (c) memory disposed on the motherboard and coupled to the processor; and, (d) a multiple phase clock generator including, (i) delay line means, coupled to receive an input clock, for generating at least two clock signals delayed a predetermined time from the input clock; (ii) edge detector means, coupled to the delay line means for generating a pulse responsive to a predetermined edge on the at least two clock signals; and, (iii) S-R means, coupled to the edge detector means, for generating at least two clock signals having a common edge and an independently adjustable second edge.

Claim 23

A method as recited in claim 16 wherein one of the at least two clock signals have a frequency (ƒ) and at least one of the at least two clock signals has a frequency which is an integer multiple of ƒ.

Claim 26

A method as recited in claim 18 wherein one of the at least two clock signals have a frequency (ƒ) and at least one of the at least two clock signals has a frequency which is an integer multiple of ƒ.