US6466071B2
Expired / Lapsed
US
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Methods and circuits for correcting a duty-cycle of a signal
Assignee: Samsung Electronics Co Ltd
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Filing: 2001-04-05
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Granted: 2002-10-15
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Expires: 2021-04-05
Abstract
Abstract A signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.
Inventors
- 👤 Kyu-hyoun Kim
- 👤 Jung-Bae Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:20
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/156; H03K5/1565; H03K5/13; H03K5/133; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; H03L2207/00; H03L2207/12; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
165 words
A method of correcting a duty-cycle of a signal, comprising: delaying the signal for a predetermined time to generate a delayed version of the signal, wherein the predetermined time is selected from the group consisting of a time in which the signal is in a first state during a single cycle of the signal and a time in which the signal is in a second state during the single cycle of the signal; and generating an output signal that transitions from the first state to the second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state, and that transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.
Claim 2
Independent Claim
165 words
A method of correcting a duty-cycle of a signal, comprising: delaying the signal for a predetermined time to generate a delayed version of the signal, wherein the predetermined time is selected from the group consisting of a time in which the signal is in a first state during a single cycle of the signal and a time in which the signal is in a second state during the single cycle of the signal; and generating an output signal that transitions from the first state to the second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state, and that transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.
Claim 3
Dependent Claim
62 words
The method of claim 1 , wherein generating the output signal comprises: inverting the delayed version of the signal to generate an inverted delayed version of the signal; limiting a slew rate of the signal to generate a first intermediate output signal; and limiting a slew rate of the inverted delayed version of the signal to generate a second intermediate output signal.
Claim 4
Dependent Claim
43 words
The method of claim 2 , wherein generating the output signal further comprises: determining a voltage difference between the first and second intermediate output signals; and generating the output signal responsive to the voltage difference between the first and second intermediate output signals.
Claim 5
Dependent Claim
69 words
The method of claim 1 , wherein delaying the signal to generate the delayed version of the signal comprises: determining a phase difference between the signal and the delayed version of the signal; generating a control voltage responsive to the phase difference between the signal and the delayed version of the signal; and delaying the signal to generate the delayed version of the signal responsive to the control voltage.
Claim 6
Dependent Claim
96 words
The method of claim 1 , wherein the output signal transitions from the first state to the second state between the transition of the signal from the first state to the second state and the transition of the delayed version of the signal from the second state to the first state, and the output signal transitions from the second state to the first state between the transition of the signal from the second state to the first state and the transition of the delayed version of the signal from the first state to the second state.
Claim 7
Independent Claim
87 words
A method of correcting a duty-cycle of a signal, comprising: limiting a slew rate of the signal to generate a first intermediate output signal; determining a voltage difference between the first intermediate output signal and a reference voltage; generating an output signal responsive to the voltage difference between first intermediate output signal and the reference voltage; delaying the output signal to generate a delayed version of the output signal; and generating the reference voltage responsive to the output signal and the delayed version of the output signal.
Claim 8
Independent Claim
87 words
A method of correcting a duty-cycle of a signal, comprising: limiting a slew rate of the signal to generate a first intermediate output signal; determining a voltage difference between the first intermediate output signal and a reference voltage; generating an output signal responsive to the voltage difference between first intermediate output signal and the reference voltage; delaying the output signal to generate a delayed version of the output signal; and generating the reference voltage responsive to the output signal and the delayed version of the output signal.
Claim 9
Dependent Claim
77 words
The method of claim 6 , wherein delaying the output signal to generate the delayed version of the output signal comprises: determining a phase difference between the output signal and the delayed version of the output signal; generating a control voltage responsive to the phase difference between the output signal and the delayed version of the output signal; and delaying the output signal to generate the delayed version of the output signal responsive to the control voltage.
Claim 10
Dependent Claim
50 words
The method of claim 6 , wherein generating the reference voltage comprises: determining a phase difference between the output signal and the delayed version of the output signal; and generating the reference voltage responsive to the phase difference between the output signal and the delayed version of the output signal.
Claim 11
Dependent Claim
170 words
A duty-cycle correction circuit, comprising: a delay circuit that is configured to generate a delayed signal for a predetermined period of time responsive to an input signal, wherein the predetermined time is selected from the group consisting of a time in which the signal is in a first state during a single cycle of the signal and a time in which the signal is in a second state during the single cycle of the signal; and a mixer circuit that is configured to generate an output signal that transitions from the first state to the second state responsive to a transition of the input signal from the first state to the second state and a transition of the delayed signal from the second state to the first state, and that transitions from the second state to the first state responsive to a transition of the input signal from the second state to the first state and a transition of the delayed signal from the first state to the second state.
Claim 12
Dependent Claim
170 words
A duty-cycle correction circuit, comprising: a delay circuit that is configured to generate a delayed signal for a predetermined period of time responsive to an input signal, wherein the predetermined time is selected from the group consisting of a time in which the signal is in a first state during a single cycle of the signal and a time in which the signal is in a second state during the single cycle of the signal; and a mixer circuit that is configured to generate an output signal that transitions from the first state to the second state responsive to a transition of the input signal from the first state to the second state and a transition of the delayed signal from the second state to the first state, and that transitions from the second state to the first state responsive to a transition of the input signal from the second state to the first state and a transition of the delayed signal from the first state to the second state.
Claim 13
Dependent Claim
32 words
The duty-cycle correction circuit of claim 9 , further comprising: a first inverter that is configured to generate an inverted delayed signal at an output terminal thereof responsive to the delayed signal.
Claim 14
Dependent Claim
87 words
The duty-cycle correction circuit of claim 10 , wherein the mixer circuit comprises: a second inverter that is configured to generate a first intermediate output signal at an output terminal thereof responsive to the input signal; a third inverter that is configured to generate a second intermediate output signal at an output terminal thereof responsive to the inverted delayed signal; and a fourth inverter that is configured to generate the output signal responsive to the first and second intermediate output signals received at an input terminal thereof.
Claim 15
Dependent Claim
55 words
The duty-cycle correction circuit of claim 10 , wherein the mixer circuit comprises: a first slew-rate limiter circuit that is configured to generate a first intermediate output signal responsive to the input signal; and a second slew-rate limiter circuit that is configured to generate a second intermediate output signal responsive to the inverted delayed signal.
Claim 16
Dependent Claim
35 words
The duty-cycle correction circuit of claim 12 , wherein the mixer circuit further comprises: a differential amplifier circuit that is configured to generate the output signal responsive to the first and second intermediate output signals.
Claim 17
Dependent Claim
77 words
The duty-cycle correction circuit of claim 9 , wherein the delay circuit comprises: a phase detector circuit that is configured to determine a phase difference between the input signal and the delayed signal; a control voltage generator circuit that is configured to generate a control voltage responsive to the phase difference between the input signal and the delayed signal; and a delay line circuit that is configured to generate the delayed signal responsive to the control voltage.
Claim 18
Dependent Claim
19 words
The duty-cycle correction circuit of claim 14 , wherein the control voltage generator circuit comprises a charge pump circuit.
Claim 19
Dependent Claim
63 words
A duty-cycle correction circuit, comprising: a differential amplifier circuit that is configured to generate an output signal responsive to an input signal and a reference voltage; a delay circuit that is configured to generate a delayed signal responsive to the output signal; and a control circuit that is configured to generate the reference voltage responsive to the output signal and the delayed signal.
Claim 20
Dependent Claim
63 words
A duty-cycle correction circuit, comprising: a differential amplifier circuit that is configured to generate an output signal responsive to an input signal and a reference voltage; a delay circuit that is configured to generate a delayed signal responsive to the output signal; and a control circuit that is configured to generate the reference voltage responsive to the output signal and the delayed signal.
Claim 21
Dependent Claim
53 words
The duty-cycle correction circuit of claim 16 , further comprising: a slew-rate limiter circuit that is configured to generate a first intermediate output signal responsive to the input signal; and wherein the differential amplifier circuit is configured to generate the output signal responsive to the first intermediate output signal and the reference voltage.
Claim 22
Dependent Claim
77 words
The duty-cycle correction circuit of claim 16 , wherein the delay circuit comprises: a phase detector circuit that is configured to determine a phase difference between the output signal and the delayed signal; a control voltage generator circuit that is configured to generate a control voltage responsive to the phase difference between the output signal and the delayed signal; and a delay line circuit that is configured to generate the delayed signal responsive to the control voltage.
Claim 23
Dependent Claim
19 words
The duty-cycle correction circuit of claim 18 , wherein the control voltage generator circuit comprises a charge pump circuit.
Claim 24
Dependent Claim
57 words
The duty-cycle correction circuit of claim 16 , wherein the control circuit comprises: a phase detector that is configured to determine a phase difference between the output signal and the delayed signal; and an integrator circuit that is configured to generate the reference voltage responsive to the phase difference between the output signal and the delayed signal.
Claim 25
Dependent Claim
17 words
The duty-cycle correction circuit of claim 20 , wherein the integrator circuit comprises a charge pump circuit.
Claim 26
Dependent Claim
17 words
The duty-cycle correction circuit of claim 21 , wherein the integrator circuit comprises a low-pass filter circuit.
Claim 27
Dependent Claim
164 words
A duty-cycle correction circuit, comprising: means for delaying a signal for a predetermined time to generate a delayed version of the signal, wherein the predetermined time is selected from the group consisting of a time in which the signal is in a first state during a single cycle of the signal and a time in which the signal is in a second state during the single cycle of the signal; and means for generating an output signal that transitions from the first state to the second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state, and that transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.
Claim 28
Dependent Claim
164 words
A duty-cycle correction circuit, comprising: means for delaying a signal for a predetermined time to generate a delayed version of the signal, wherein the predetermined time is selected from the group consisting of a time in which the signal is in a first state during a single cycle of the signal and a time in which the signal is in a second state during the single cycle of the signal; and means for generating an output signal that transitions from the first state to the second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state, and that transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.
Claim 29
Dependent Claim
73 words
The duty-cycle correction circuit of claim 23 , wherein the means for generating the output signal comprises: means for inverting the delayed version of the signal to generate an inverted delayed version of the signal; means for limiting a slew rate of the signal to generate a first intermediate output signal; and means for limiting a slew rate of the inverted delayed version of the signal to generate a second intermediate output signal.
Claim 30
Dependent Claim
52 words
The duty-cycle correction circuit of claim 24 , wherein the means for generating the output signal further comprises: means for determining a voltage difference between the first and second intermediate output signals; and means for generating the output signal responsive to the voltage difference between the first and second intermediate output signals.
Claim 31
Dependent Claim
80 words
The duty-cycle correction circuit of claim 23 , wherein the means for delaying the signal to generate the delayed version of the signal comprises: means for determining a phase difference between the signal and the delayed version of the signal; means for generating a control voltage responsive to the phase difference between the signal and the delayed version of the signal; and means for delaying the signal to generate the delayed version of the signal responsive to the control voltage.
Claim 32
Dependent Claim
98 words
The duty-cycle correction circuit of claim 23 , wherein the output signal transitions from the first state to the second state between the transition of the signal from the first state to the second state and the transition of the delayed version of the signal from the second state to the first state, and the output signal transitions from the second state to the first state between the transition of the signal from the second state to the first state and the transition of the delayed version of the signal from the first state to the second state.
Claim 33
Dependent Claim
92 words
A duty-cycle correction circuit, comprising: means for limiting a slew rate of a signal to generate a first intermediate output signal; means for determining a voltage difference between the first intermediate output signal and a reference voltage; means for generating an output signal responsive to the voltage difference between first intermediate output signal and the reference voltage; means for delaying the output signal to generate a delayed version of the output signal; and means for generating the reference voltage responsive to the output signal and the delayed version of the output signal.
Claim 34
Dependent Claim
92 words
A duty-cycle correction circuit, comprising: means for limiting a slew rate of a signal to generate a first intermediate output signal; means for determining a voltage difference between the first intermediate output signal and a reference voltage; means for generating an output signal responsive to the voltage difference between first intermediate output signal and the reference voltage; means for delaying the output signal to generate a delayed version of the output signal; and means for generating the reference voltage responsive to the output signal and the delayed version of the output signal.
Claim 35
Dependent Claim
88 words
The duty-cycle correction circuit of claim 28 , wherein the means for delaying the output signal to generate the delayed version of the output signal comprises: means for determining a phase difference between the output signal and the delayed version of the output signal; means for generating a control voltage responsive to the phase difference between the output signal and the delayed version of the output signal; and means for delaying the output signal to generate the delayed version of the output signal responsive to the control voltage.
Claim 36
Dependent Claim
59 words
The duty-cycle correction circuit of claim 28 , wherein the means for generating the reference voltage comprises: means for determining a phase difference between the output signal and the delayed version of the output signal; and means for generating the reference voltage responsive to the phase difference between the output signal and the delayed version of the output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-14 | 2006-04-15 | 2006-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-14 | 2010-04-15 | 2010-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-14 | 2014-04-15 | 2014-10-15 | $7700.00 | Window Closed / Lapsed |