US5572158A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplifier with active duty cycle correction
Assignee: Rambus Inc
•
Filing: 1995-09-18
•
Granted: 1996-11-05
•
Expires: 2015-09-18
Abstract
Abstract A circuit is provided which actively corrects the duty cycle of a periodic signal such as a clock signal. The amplifier circuit includes a duty cycle error measurement circuit which measures the error of the output signal from a predetermined duty cycle, for example, 50% duty cycle. A correcting signal is generated from the error signal output by the duty cycle error measurement circuit. The correcting signal is combined with the uncorrected input signal to the circuit to function to offset the signal in order to correct the duty cycle, the combined signals are input to an integrating capacitance to generate a slew limited signal. By varying the amount of the correcting signal and therefore the symmetry of the slew limited signal, the duty cycle of the output can be varied to generate a signal with the desired duty cycle.
Inventors
- 👤 Thomas H. Lee
- 👤 Kevin S. Donnelly
- 👤 Tsyr-Chyang Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:50
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/082; H03K5/086
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
167 words
An amplifier circuit with active duty cycle correction of an input signal to generate a corrected output signal, said amplifier comprising: a first amplifier receiving an input representative of an uncorrected input signal and generating as output an uncorrected output signal; a duty cycle measurement circuit which measures the corrected output signal and generates as an output a difference signal representative of the difference of the duty cycle of the corrected output signal and a predetermined duty cycle; a second amplifier which receives as input the output of the duty cycle measurement circuit and generates a correction signal; summing means for summing the correction signal and the uncorrected output signal to produce a summed signal; an integrating capacitance which receives as input the summed signal and generates as output a slew limited voltage signal, said integrating capacitance causing the output to be slew limited for a portion of the input greater than the predetermined duty cycle, said slew limited voltage signal representative of the corrected output signal.
Claim 2
Dependent Claim
167 words
An amplifier circuit with active duty cycle correction of an input signal to generate a corrected output signal, said amplifier comprising: a first amplifier receiving an input representative of an uncorrected input signal and generating as output an uncorrected output signal; a duty cycle measurement circuit which measures the corrected output signal and generates as an output a difference signal representative of the difference of the duty cycle of the corrected output signal and a predetermined duty cycle; a second amplifier which receives as input the output of the duty cycle measurement circuit and generates a correction signal; summing means for summing the correction signal and the uncorrected output signal to produce a summed signal; an integrating capacitance which receives as input the summed signal and generates as output a slew limited voltage signal, said integrating capacitance causing the output to be slew limited for a portion of the input greater than the predetermined duty cycle, said slew limited voltage signal representative of the corrected output signal.
Claim 3
Dependent Claim
35 words
The amplifier as set forth in claim 1, further comprising a third amplifier which receives as input the slew limited voltage signal and generates as output a square waveform representative of the corrected output signal.
Claim 4
Dependent Claim
30 words
The amplifier as set forth in claim 1, further comprising a signal clamp means coupled to the integrating capacitance to clamp the slew limited voltage signal to a predetermined voltage.
Claim 5
Dependent Claim
42 words
The amplifier as set forth in claim 3, wherein said signal clamp means functions to clamp the output such that the slew limited voltage signal exhibits substantial slew limiting for a fraction of the input signal greater than the predetermined duty cycle.
Claim 6
Dependent Claim
22 words
The amplifier as set forth in claim 1, wherein said duty cycle measurement circuit further filters ripple from the corrected output signal.
Claim 7
Dependent Claim
30 words
The amplifier as set forth in claim 5, wherein said duty cycle measurement circuit filters ripple by adding extra poles to a transfer function of the duty cycle measurement circuit.
Claim 8
Dependent Claim
17 words
The amplifier as set forth in claim 1, wherein said first and second amplifiers comprise transconductance amplifiers.
Claim 9
Dependent Claim
20 words
The amplifier as set forth in claim 1, wherein said duty cycle error measurement circuit comprises a differential charge pump.
Claim 10
Dependent Claim
20 words
The amplifier circuit as set forth in claim 1, wherein said input signal is representative of a differential input signal.
Claim 11
Dependent Claim
21 words
The amplifier circuit as set forth in claim 1, wherein said output of the first amplifier comprises a differential output signal.
Claim 12
Dependent Claim
28 words
The amplifier circuit as set forth in claim 2, further comprising an inverter coupled to receive the output of the third amplifier and output the corrected output signal.
Claim 13
Dependent Claim
179 words
An amplifier with active duty cycle correction of an input signal to generate a corrected output signal, said amplifier circuit comprising: a first amplifier means receiving a first and second input representative of a differential uncorrected input signal and generating as output a differential output current; a duty cycle measurement means which measures the corrected output signal and generates as an output a differential signal representative of the difference of the duty cycle of the corrected output signal and a predetermined duty cycle; a second amplifier means which receives as input the output of the duty cycle measurement means and generates a correction current; summing means for summing the correction current and the differential output current to produce differential summed current signals; an integrating capacitance means which receives as input the summed differential current and generates as output a slew limited differential voltage signal, said integrating capacitance means causing the output to be slew limited for a portion of the input greater than the predetermined duty cycle, said slew limited differential voltage signal representative of the corrected output signal.
Claim 14
Dependent Claim
179 words
An amplifier with active duty cycle correction of an input signal to generate a corrected output signal, said amplifier circuit comprising: a first amplifier means receiving a first and second input representative of a differential uncorrected input signal and generating as output a differential output current; a duty cycle measurement means which measures the corrected output signal and generates as an output a differential signal representative of the difference of the duty cycle of the corrected output signal and a predetermined duty cycle; a second amplifier means which receives as input the output of the duty cycle measurement means and generates a correction current; summing means for summing the correction current and the differential output current to produce differential summed current signals; an integrating capacitance means which receives as input the summed differential current and generates as output a slew limited differential voltage signal, said integrating capacitance means causing the output to be slew limited for a portion of the input greater than the predetermined duty cycle, said slew limited differential voltage signal representative of the corrected output signal.
Claim 15
Dependent Claim
32 words
The amplifier as set forth in claim 12, further comprising a signal clamping means coupled to the integrating capacitance means to clamp the slew limited differential voltage signal to a predetermined voltage.
Claim 16
Dependent Claim
42 words
The amplifier as set forth in claim 13, wherein said signal clamping means functions to clamp the output such that the slew limited voltage signal exhibits substantial slew limiting for a fraction of the input signal greater than the predetermined duty cycle.
Claim 17
Dependent Claim
22 words
The amplifier as set forth in claim 13, wherein said duty cycle measurement means further filters ripple from the corrected output signal.
Claim 18
Dependent Claim
30 words
The amplifier as set forth in claim 15, wherein said duty cycle measurement means filters ripple by adding extra poles to a transfer function of the duty cycle measurement means.
Claim 19
Independent Claim
150 words
A method for actively correcting the duty cycle of an uncorrected input signal to generate a corrected output signal, said method comprising the steps of: measuring the duty cycle of the corrected output signal and generating as an output a signal representative of the difference of the duty cycle of the corrected output signal and a predetermined duty cycle; generating a correction signal from the signal representative of the difference of the duty cycle of the corrected output signal and a predetermined duty cycle; generating an uncorrected output signal from said uncorrected input signal summing the correction signal and uncorrected output signal to produce a summed signal; generating a slew limited voltage signal from the summed signal, said slew limited voltage signal being slew limited for a portion of the uncorrected input signal greater than the predetermined duty cycle, said slew limited voltage signal representative of the corrected output signal.
Claim 20
Independent Claim
150 words
A method for actively correcting the duty cycle of an uncorrected input signal to generate a corrected output signal, said method comprising the steps of: measuring the duty cycle of the corrected output signal and generating as an output a signal representative of the difference of the duty cycle of the corrected output signal and a predetermined duty cycle; generating a correction signal from the signal representative of the difference of the duty cycle of the corrected output signal and a predetermined duty cycle; generating an uncorrected output signal from said uncorrected input signal summing the correction signal and uncorrected output signal to produce a summed signal; generating a slew limited voltage signal from the summed signal, said slew limited voltage signal being slew limited for a portion of the uncorrected input signal greater than the predetermined duty cycle, said slew limited voltage signal representative of the corrected output signal.
Claim 21
Dependent Claim
31 words
The method as set forth in claim 17, further comprising the step of generating as output a square waveform representative of the corrected output signal from the slew limited voltage signal.
Claim 22
Dependent Claim
23 words
The method as set forth in claim 17, further comprising the step of clamping the slew limited voltage signal to a predetermined voltage.
Claim 23
Dependent Claim
31 words
The method as set forth in claim 17 wherein the slew limited voltage signal exhibits substantial slew limiting for a fraction of the input signal greater than the predetermined duty cycle.
Claim 24
Dependent Claim
31 words
The method as set forth in claim 17, further comprising the step of filtering ripple from the corrected output signal prior to measuring the duty cycle of the corrected output signal.
References Cited (Backward Citations)
US4789799A
Cited
US4644196A
Cited
US4724337A
Cited
DE3816973A1
Cited
EP0343899A2
Cited
US4992757A
Cited
EP0398751A2
Cited
DE4018615A1
Cited
US5182476A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |