US6636098B1
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US
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Differential integrator and related circuitry
Assignee: Rambus Inc
•
Filing: 2001-12-05
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Granted: 2003-10-21
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Expires: 2021-12-05
Abstract
Abstract An improved differential integrator and related circuitry is disclosed. In one exemplary embodiment, the improved differential integrator comprises an integrating gain boosted cascode circuit for receiving an input signal having a first locking time and for generating an output signal having a second locking time, wherein the second locking time being delayed by a predetermined amount from the first locking time. The improved differential integrator may also comprise a multi-node common-mode feedback circuit, and a dynamic cascode common-mode feedback circuit. The integrating gain boosted cascode circuit may include a gain boosted cascode structure and a capacitor compensation structure. The multi-node common-mode feedback circuit may include a folded cascode circuit. The dynamic cascode common-mode feedback circuit may include a cascode circuit that uses common-mode feedback.
Inventors
- 👤 Jade Kizer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:55
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45183; H03F3/45192; H03F3/45479; H03F3/45632; H03F3/45636; H03F3/45641; H03F3/4565; H03F3/45654; H03F3/45659; H03F2203/00; H03F2203/45; H03F2203/45028; H03F2203/45352; H03F2203/45356; H03F2203/45466; H03F2203/45642
Claims Analysis
Total Claims: 68
Claim 1
Independent Claim
60 words
An improved differential integrator comprising: an integrating gain boosted cascode circuit for receiving an input signal having a bandwidth and for generating an output signal, the integrating gain boosted cascode circuit operating slower than the bandwidth of the input signal but faster than a lock time of the improved differential integrator so as to reduce offset in the output signal.
Claim 2
Dependent Claim
60 words
An improved differential integrator comprising: an integrating gain boosted cascode circuit for receiving an input signal having a bandwidth and for generating an output signal, the integrating gain boosted cascode circuit operating slower than the bandwidth of the input signal but faster than a lock time of the improved differential integrator so as to reduce offset in the output signal.
Claim 3
Dependent Claim
44 words
The improved differential integrator of claim 1 , further comprising: a multi-node common-mode feedback circuit, coupled to the integrating gain boosted cascode circuit, for receiving at least one bias signal and for reducing offset in a desired common-mode of the output signal based thereon.
Claim 4
Dependent Claim
51 words
The improved differential integrator of claim 2 , further comprising: a dynamic cascode common-mode feedback circuit, coupled to the integrating gain boosted cascode circuit and the multi-node common-mode feedback circuit, for comparing the output signal and a reference voltage and for generating the at least one bias signal in response thereto.
Claim 5
Dependent Claim
60 words
The improved differential integrator of claim 2 , further comprising: a nap mode circuit, coupled to the integrating gain boosted cascode circuit and the multi-node common-mode feedback circuit, for receiving a feedback signal and a nap signal and for determining a sleep mode based thereon, wherein a differential charge associated with the output signal is stored during the sleep mode.
Claim 6
Dependent Claim
86 words
The improved differential integrator of claim 2 , wherein the multi-node common-mode feedback circuit comprises: common-mode feedback circuitry for determining a difference between an input voltage and a reference voltage and for adjusting at least one current branch based on the difference; and at least one current source, coupled to the common-mode feedback circuitry, for receiving at least one current signal via the at least one current branch; wherein a first current branch and a second current branch are adjusted simultaneously to compensate for common-mode correction.
Claim 7
Dependent Claim
76 words
The improved differential integrator of claim 3 , wherein the dynamic cascode common-mode feedback circuit comprises: common-mode feedback circuitry for receiving an input signal and a reference signal, for determining a difference between the input signal and the reference signal, and for generating a first bias signal for driving a cascoded current source and a second bias signal that varies dynamically with the first bias signal for driving a second current source based upon the difference.
Claim 8
Dependent Claim
72 words
The improved differential integrator of claim 4 , wherein the nap mode circuit comprises: logic circuitry for receiving the nap signal and the feedback signal and for determining the sleep mode based thereon; and storage circuitry, coupled to the logic circuitry, for storing the differential charge by disconnecting a differential path during the sleep mode; wherein a differential voltage is held constant prior to a wake-up mode to shorten a wake-up time.
Claim 9
Dependent Claim
37 words
The improved differential integrator of claim 1 , further comprising: a level shifter circuit, coupled to the integrating gain boosted cascode circuit, for level shifting the output signal so as to generate a level shifted output signal.
Claim 10
Dependent Claim
110 words
The improved differential integrator of claim 8 , wherein the level shifter circuit comprises: first charge storage circuitry for receiving differential signals at an input node; charge pump circuitry, coupled to the first charge storage circuitry, for level shifting the differential signals and for generating level shifted differential signals; second charge storage circuitry, coupled to the charge pump circuitry, for storing the level shifted differential signals and for generating output signals to an output node based thereon; and at least one pair of switches coupled to the charge pump circuitry for enabling charge to flow between the input node and the output node so as to establish an equilibrium therebetween.
Claim 11
Dependent Claim
52 words
The improved differential integrator of claim 1 , wherein the integrating gain boosted cascode circuit is a first integrating gain boosted cascode circuit, further comprising: a second integrating gain boosted cascode circuit, coupled to an output node of the first integrating gain boosted cascode circuit, for generating a pair of output signals.
Claim 12
Dependent Claim
88 words
The improved differential integrator of claim 1 , wherein the integrating gain boosted cascode circuit comprises: a gain boosted cascode structure for receiving substantially equal input voltages and for generating a differential voltage to compensate for channel length modulation; and a capacitor compensation circuit, coupled to an output of the gain boosted cascode structure, for generating an output slew rate of the differential voltage which is slower than an input slew rate of the input voltages such that the differential voltage is a time-averaged gain boosted differential voltage.
Claim 13
Dependent Claim
79 words
An integrating gain boosted cascode circuit comprising: a gain boosted cascode structure for receiving substantially equal input voltages and for generating a differential voltage to compensate for channel length modulation; and a capacitor compensation circuit, coupled to an output of the gain boosted cascode structure, for generating an output slew rate of the differential voltage which is slower than an input slew rate of the input voltages such that the differential voltage is a time-averaged gain boosted differential voltage.
Claim 14
Dependent Claim
79 words
An integrating gain boosted cascode circuit comprising: a gain boosted cascode structure for receiving substantially equal input voltages and for generating a differential voltage to compensate for channel length modulation; and a capacitor compensation circuit, coupled to an output of the gain boosted cascode structure, for generating an output slew rate of the differential voltage which is slower than an input slew rate of the input voltages such that the differential voltage is a time-averaged gain boosted differential voltage.
Claim 15
Dependent Claim
36 words
The integrating gain boosted cascode circuit of claim 12 , further comprising: a cascode structure, coupled to an output node of the gain boosted cascode structure, for increasing output resistance of the gain boosted cascode structure.
Claim 16
Dependent Claim
41 words
The integrating gain boosted cascode circuit of claim 12 , further comprising: a cascode structure, coupled to an output node of the gain boosted cascode structure, for providing a feedback path from the cascode structure to the gain boosted cascode structure.
Claim 17
Dependent Claim
35 words
The integrating gain boosted cascode circuit of claim 12 , further comprising: a current source, coupled to an input node of the gain boosted cascode structure, for providing current to the gain boosted cascode structure.
Claim 18
Dependent Claim
50 words
The integrating gain boosted cascode circuit of claim 12 , wherein the gain boosted cascode structure is a first gain boosted cascode structure, further comprising: a second gain boosted cascode structure, coupled to an output node of the first gain boosted cascode structure, for generating a pair of output signals.
Claim 19
Dependent Claim
33 words
The integrating gain boosted cascode circuit of claim 16 , further comprising: a differential pair, coupled to an input node of the first gain boosted cascode structure, for providing a differential voltage-to-current conversion.
Claim 20
Dependent Claim
19 words
The integrating gain boosted cascode circuit of claim 12 , wherein the gain boosted cascode structure comprises an op-amp.
Claim 21
Dependent Claim
42 words
The integrating gain boosted cascode circuit of claim 12 , further comprising: a level shifter circuit, coupled to the output of the gain boosted cascode structure, for level shifting the differential voltage so as to generate a level shifted differential output signal.
Claim 22
Dependent Claim
77 words
A multi-node common-mode feedback circuit comprising: common-mode feedback circuitry for determining a difference between an input voltage and a reference voltage and for adjusting at least one current branch based on the difference; and at least one current source, coupled to the common-mode feedback circuitry, for receiving at least one current signal via the at least one current branch; wherein a first current branch and a second current branch are adjusted simultaneously to compensate for common-mode correction.
Claim 23
Dependent Claim
77 words
A multi-node common-mode feedback circuit comprising: common-mode feedback circuitry for determining a difference between an input voltage and a reference voltage and for adjusting at least one current branch based on the difference; and at least one current source, coupled to the common-mode feedback circuitry, for receiving at least one current signal via the at least one current branch; wherein a first current branch and a second current branch are adjusted simultaneously to compensate for common-mode correction.
Claim 24
Dependent Claim
51 words
The multi-node common-mode feedback circuit of claim 20 , further comprising: a first current source coupled to the first current branch; a second current source coupled to the second current branch; and a differential pair circuit, coupled to the first current source and the second current source, for providing voltage-to-current conversion.
Claim 25
Dependent Claim
37 words
The multi-node common-mode feedback circuit of claim 20 , further comprising: a differential pair circuit, coupled to at least one of a first current source and a second current source, for generating a pair of output signals.
Claim 26
Dependent Claim
23 words
The multi-node common-mode feedback circuit of claim 22 , wherein the pair of output signals are fed back to the common-mode feedback circuitry.
Claim 27
Dependent Claim
37 words
The multi-node common-mode feedback circuit of claim 20 , wherein the first current branch is adjusted in a first direction and the second current branch is adjusted in a second direction substantially opposite to the first direction.
Claim 28
Dependent Claim
25 words
The multi-node common-mode feedback circuit of claim 20 , wherein the first current branch and the second current branch are adjusted in a first direction.
Claim 29
Dependent Claim
42 words
The multi-node common-mode feedback circuit of claim 25 , wherein the common-mode feedback circuit has a third current branch, further comprising: a current source coupled to the third current branch, wherein the third current branch is fixed at a predetermined DC value.
Claim 30
Dependent Claim
47 words
The multi-node common-mode feedback circuit of claim 25 , wherein the common-mode feedback circuitry has a third current branch, further comprising: a current source coupled to the third current branch, wherein the third current branch is adjusted in a second direction substantially opposite to the first direction.
Claim 31
Dependent Claim
21 words
The multi-node common-mode feedback circuit of claim 20 , wherein the common-mode feedback circuitry is implemented in a folded cascode structure.
Claim 32
Dependent Claim
20 words
The multi-node common-mode feedback circuit of claim 20 , wherein the common-mode feedback circuitry is implemented in an op-amp structure.
Claim 33
Dependent Claim
67 words
A dynamic cascode common-mode feedback circuit comprising: common-mode feedback circuitry for receiving an input signal and a reference signal, for determining a difference between the input signal and the reference signal, and for generating a first bias signal for driving a cascoded current source and a second bias signal that varies dynamically with the first bias signal for driving a second current source based upon the difference.
Claim 34
Dependent Claim
67 words
A dynamic cascode common-mode feedback circuit comprising: common-mode feedback circuitry for receiving an input signal and a reference signal, for determining a difference between the input signal and the reference signal, and for generating a first bias signal for driving a cascoded current source and a second bias signal that varies dynamically with the first bias signal for driving a second current source based upon the difference.
Claim 35
Dependent Claim
28 words
The dynamic cascode common-mode feedback circuit of claim 30 , wherein the cascoded current source operates in an operating region for a predetermined range of common-mode feedback bias.
Claim 36
Dependent Claim
21 words
The dynamic cascode common-mode feedback circuit of claim 30 , wherein the cascoded current source is implemented in a pull-down network.
Claim 37
Dependent Claim
21 words
The dynamic cascode common-mode feedback circuit of claim 32 , wherein the pull-down network circuitry is coupled to a pull-up network.
Claim 38
Dependent Claim
63 words
A nap mode circuit comprising: logic circuitry for receiving a nap signal and a feedback signal and for determining a sleep mode based thereon; and storage circuitry, coupled to the logic circuitry, for storing a differential charge by disconnecting a differential path during the sleep mode; wherein a differential voltage is held constant prior to a wake-up mode to shorten a wake-up time.
Claim 39
Dependent Claim
63 words
A nap mode circuit comprising: logic circuitry for receiving a nap signal and a feedback signal and for determining a sleep mode based thereon; and storage circuitry, coupled to the logic circuitry, for storing a differential charge by disconnecting a differential path during the sleep mode; wherein a differential voltage is held constant prior to a wake-up mode to shorten a wake-up time.
Claim 40
Dependent Claim
28 words
The nap mode circuit of claim 34 , wherein the nap signal is logically NORed with the feedback signal to detect clock data presence before the wake-up mode.
Claim 41
Dependent Claim
20 words
The nap mode circuit of claim 34 , further comprising: at least one foot transistor for breaking the differential path.
Claim 42
Dependent Claim
106 words
A level shifter circuit for level shifting differential signals comprising: first charge storage circuitry for receiving differential signals at an input node; charge pump circuitry, coupled to the first charge storage circuitry, for level shifting the differential signals and for generating level shifted differential signals; second charge storage circuitry, coupled to the charge pump circuitry, for storing the level shifted differential signals and for generating output signals to an output node based thereon; and at least one pair of switches coupled to the charge pump circuitry for enabling charge to flow between the input node and the output node so as to establish an equilibrium therebetween.
Claim 43
Dependent Claim
106 words
A level shifter circuit for level shifting differential signals comprising: first charge storage circuitry for receiving differential signals at an input node; charge pump circuitry, coupled to the first charge storage circuitry, for level shifting the differential signals and for generating level shifted differential signals; second charge storage circuitry, coupled to the charge pump circuitry, for storing the level shifted differential signals and for generating output signals to an output node based thereon; and at least one pair of switches coupled to the charge pump circuitry for enabling charge to flow between the input node and the output node so as to establish an equilibrium therebetween.
Claim 44
Dependent Claim
19 words
The level shifter circuit of claim 37 , wherein the at least one pair of switches are pass gates.
Claim 45
Dependent Claim
52 words
The level shifter circuit of claim 37 , wherein the at least one pair of switches includes a first pair of switches coupled between the first charge storage circuitry and the charge pump circuitry and a second pair of switches coupled between the second charge storage circuitry and the charge pump circuitry.
Claim 46
Dependent Claim
19 words
The level shifter circuit of claim 39 , wherein the first pair of switches operate with a first phase.
Claim 47
Dependent Claim
25 words
The level shifter circuit of claim 40 , wherein the second pair of switches operate with a second phase substantially opposite to the first phase.
Claim 48
Dependent Claim
23 words
The level shifter circuit of claim 37 , wherein the differential signals include first differential signals that are level shifted with common-mode noise.
Claim 49
Dependent Claim
19 words
The level shifter circuit of claim 37 , wherein low-noise DC level shifted differential signals for low voltage applications.
Claim 50
Dependent Claim
24 words
The level shifter circuit of claim 37 , wherein the charge pump circuitry has a linear capacitor for pumping the first charge storage circuitry.
Claim 51
Dependent Claim
16 words
The level shifter circuit of claim 44 , wherein the linear capacitor is a metal-insulator-metal capacitor.
Claim 52
Dependent Claim
18 words
The level shifter circuit of claim 44 , wherein the linear capacitor is a depletion mode CMOS capacitor.
Claim 53
Dependent Claim
21 words
The level shifter circuit of claim 37 , wherein the first charge storage circuitry is voltage threshold insensitive charge storage circuitry.
Claim 54
Dependent Claim
22 words
The level shifter circuit of claim 37 , wherein the first charge storage circuitry has at least one complementary CMOS gate capacitor.
Claim 55
Dependent Claim
20 words
The level shifter circuit of claim 37 , wherein the first charge storage circuitry has at least one metal-insulator-metal capacitor.
Claim 56
Dependent Claim
21 words
The level shifter circuit of claim 37 , wherein the first charge storage circuitry has at least one depletion-mode CMOS capacitor.
Claim 57
Independent Claim
107 words
A method for reducing offset in a desired common-mode of an output signal of a differential integrator, the method comprising the steps of: receiving an input signal having a bandwidth; generating an output signal based upon the input signal, the output signal being generated slower than the bandwidth of the input signal but faster than a lock time of the differential integrator; comparing the output signal and a reference voltage; generating at least one bias signal based at least in part upon the comparison; and reducing offset in a desired common-mode of the output signal based at least in part upon the at least one bias signal.
Claim 58
Independent Claim
107 words
A method for reducing offset in a desired common-mode of an output signal of a differential integrator, the method comprising the steps of: receiving an input signal having a bandwidth; generating an output signal based upon the input signal, the output signal being generated slower than the bandwidth of the input signal but faster than a lock time of the differential integrator; comparing the output signal and a reference voltage; generating at least one bias signal based at least in part upon the comparison; and reducing offset in a desired common-mode of the output signal based at least in part upon the at least one bias signal.
Claim 59
Independent Claim
77 words
A method for generating a time-average gain boosted differential voltage in an integrating gain boosted cascode circuit, the method comprising the steps of: receiving substantially equal input voltages; generating a differential voltage, based upon the input voltages, to compensate for channel length modulation; and generating an output slew rate of the differential voltage which is slower than an input slew rate of the input voltages such that the differential voltage is a time-averaged gain boosted differential voltage.
Claim 60
Independent Claim
77 words
A method for generating a time-average gain boosted differential voltage in an integrating gain boosted cascode circuit, the method comprising the steps of: receiving substantially equal input voltages; generating a differential voltage, based upon the input voltages, to compensate for channel length modulation; and generating an output slew rate of the differential voltage which is slower than an input slew rate of the input voltages such that the differential voltage is a time-averaged gain boosted differential voltage.
Claim 61
Independent Claim
72 words
A method for compensating for common-mode correction in a multi-node common-mode feedback circuit, the method comprising the steps of: determining a difference between an input voltage and a reference voltage; adjusting at least one current branch based on the difference; and receiving at least one current signal via the at least one current branch, wherein a first current branch and a second current branch are adjusted simultaneously to compensate for common-mode correction.
Claim 62
Independent Claim
72 words
A method for compensating for common-mode correction in a multi-node common-mode feedback circuit, the method comprising the steps of: determining a difference between an input voltage and a reference voltage; adjusting at least one current branch based on the difference; and receiving at least one current signal via the at least one current branch, wherein a first current branch and a second current branch are adjusted simultaneously to compensate for common-mode correction.
Claim 63
Independent Claim
75 words
A method for generating a constant overdrive voltage in a dynamic cascode common-mode feedback circuit, the method comprising the steps of: receiving an input signal and a reference signal; determining a difference between the input signal and the reference signal, and generating a first bias signal for driving a cascoded current source and a second bias signal that varies dynamically with the first bias signal for driving a second current source based upon the difference.
Claim 64
Independent Claim
75 words
A method for generating a constant overdrive voltage in a dynamic cascode common-mode feedback circuit, the method comprising the steps of: receiving an input signal and a reference signal; determining a difference between the input signal and the reference signal, and generating a first bias signal for driving a cascoded current source and a second bias signal that varies dynamically with the first bias signal for driving a second current source based upon the difference.
Claim 65
Independent Claim
65 words
A method for implementing a nap circuit, the method comprising the steps of: receiving a nap signal and a feedback signal; determining a sleep mode based upon the nap signal and the feedback signal; and storing a differential charge by disconnecting a differential path during the sleep mode, wherein a differential voltage is held constant prior to a wake-up mode to shorten a wake-up time.
Claim 66
Independent Claim
65 words
A method for implementing a nap circuit, the method comprising the steps of: receiving a nap signal and a feedback signal; determining a sleep mode based upon the nap signal and the feedback signal; and storing a differential charge by disconnecting a differential path during the sleep mode, wherein a differential voltage is held constant prior to a wake-up mode to shorten a wake-up time.
Claim 67
Independent Claim
66 words
A method for level shifting differential signals, the method comprising the steps of: receiving differential signals at an input node; level shifting the differential signals; storing the level shifted differential signals; generating output signals to an output node based upon the stored level shifted differential signals; and enabling charge to flow between the input node and the output node so as to establish an equilibrium therebetween.
Claim 68
Independent Claim
66 words
A method for level shifting differential signals, the method comprising the steps of: receiving differential signals at an input node; level shifting the differential signals; storing the level shifted differential signals; generating output signals to an output node based upon the stored level shifted differential signals; and enabling charge to flow between the input node and the output node so as to establish an equilibrium therebetween.
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