Duty-cycle regulator

Claim 1

A duty-cycle regulation method for deriving an output clock signal having a predetermined duty cycle from an input clock signal having an arbitrary duty cycle comprising the steps of: a) receiving the input clock signal; b) switching an output clock storage element to a first state upon detecting a transition in the input clock signal for driving the output clock signal to a first signal level; and, c) switching the output :clock storage element to a second state after a delay interval equal to a fraction of the period of the input clock signal for driving the output clock signal to a second signal level, said delay interval being determined by the steps of, i) generating a delay control signal from a low-pass filter, ii) feeding electric charges from a first charge pump into said low-pass filter, iii) draining electric charges out of said low-pass filter, iv) turning said first charge pump and a second charge pump alternately on and off in accordance with the output clock storage element switching between the first and second states respectively, and, v) making an interval between the output clock signal changing to the first signal level and the delay control signal reaching a predetermined threshold as the delay interval.