US5008636A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for low skew system clock distribution and generation of 2X frequency clocks
Assignee: HP Inc
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Filing: 1988-10-28
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Granted: 1991-04-16
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Expires: 2008-10-28
Abstract
Abstract A clock generation circuit on each circuit board of a computer system and which removes board-to-board system skew in clock signal distribution. A phase-locked loop is employed to maintain synchronization between the system reference clock signal distributed to each board and the outputs of the distribution gate array in the generation circuit on each board. A 2X frequency clock is provided by combining the clock signal with a delayed version of itself. A second order loop is employed to monitor the duty cycle of the 2X frequency clock and to adjust the duty cycle of the regular frequency clock to provide cycle-to-cycle symmetry for the 2X frequency clock.
Inventors
- 👤 Scott Markinson
- 👤 Michael Schuster
- 👤 Thomas Hogan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:08
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F1/06; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
193 words
Apparatus for generation of a plurality of synchronized clock signals on a computer system circuit board from a reference clock signal comprising: means for receiving a reference clock signal; means for providing a clock signal whose frequency may be varied in response to a control signal; means, receiving said clock signal, for providing a plurality of clock output signals having a selected phase relationship therebetween and having a delay from said reference clock signal; phase-locked loop means receiving said reference clock signal and a selected one of said plurality of clock output signals, for providing a control signal to said clock signal providing means, for varying the frequency of said plurality of clock output signals, to maintain a phase relationship between said plurality of clock output signals and said reference clock signal and to compensate for said delay; frequency multiplier means, receiving said clock signal, for providing an output signal at a frequency being a multiple of said clock signal, and comprising plural clock pulses each having a specified duty cycle relative to said clock signal; and duty cycle control means for controlling the duty cycle of each of said plural clock pulses.
Claim 2
Dependent Claim
193 words
Apparatus for generation of a plurality of synchronized clock signals on a computer system circuit board from a reference clock signal comprising: means for receiving a reference clock signal; means for providing a clock signal whose frequency may be varied in response to a control signal; means, receiving said clock signal, for providing a plurality of clock output signals having a selected phase relationship therebetween and having a delay from said reference clock signal; phase-locked loop means receiving said reference clock signal and a selected one of said plurality of clock output signals, for providing a control signal to said clock signal providing means, for varying the frequency of said plurality of clock output signals, to maintain a phase relationship between said plurality of clock output signals and said reference clock signal and to compensate for said delay; frequency multiplier means, receiving said clock signal, for providing an output signal at a frequency being a multiple of said clock signal, and comprising plural clock pulses each having a specified duty cycle relative to said clock signal; and duty cycle control means for controlling the duty cycle of each of said plural clock pulses.
Claim 3
Dependent Claim
40 words
The apparatus of claim 1, wherein: said frequency multiplier means output signal comprises two clock pulses corresponding to each clock signal; and said duty cycle control means provides a substantially equal duty cycle to each of said two clock pulses.
Claim 4
Dependent Claim
166 words
Apparatus for distributing clock signals in a computer system comprising: means for generating a reference clock signal; and a plurality of duplication means, receiving said reference clock signal, for generating a plurality of clock output signals having a selected phase relationship with said reference clock signal, each of said duplication means including: means for receiving said reference clock signal; means for generating a clock signal whose frequency may be varied in response to a control signal; means, receiving said clock signal, for providing a plurality of clock output signals having a selective phase relationship therebetween, and having a delay from said reference clock signal; and phase-locked loop means receiving said reference clock signal and a selected one of said plurality of clock output signals, for providing a control signal to said clock signal generating means, for varying the frequency of said clock signal to maintain a phase relationship between said plurality of clock output signals and said reference clock signal, and to compensate for said delay.
Claim 5
Dependent Claim
166 words
Apparatus for distributing clock signals in a computer system comprising: means for generating a reference clock signal; and a plurality of duplication means, receiving said reference clock signal, for generating a plurality of clock output signals having a selected phase relationship with said reference clock signal, each of said duplication means including: means for receiving said reference clock signal; means for generating a clock signal whose frequency may be varied in response to a control signal; means, receiving said clock signal, for providing a plurality of clock output signals having a selective phase relationship therebetween, and having a delay from said reference clock signal; and phase-locked loop means receiving said reference clock signal and a selected one of said plurality of clock output signals, for providing a control signal to said clock signal generating means, for varying the frequency of said clock signal to maintain a phase relationship between said plurality of clock output signals and said reference clock signal, and to compensate for said delay.
Claim 6
Dependent Claim
36 words
The apparatus of claim 3, wherein: said selected one of said plurality of clock output signals has a delay from said received reference clock signal different from the remainder of said plurality of clock output signals.
Claim 7
Dependent Claim
30 words
The apparatus of claim 3, including: frequency multiplier means, for receiving said clock signal, and for providing an output signal with a frequency being a multiple of said clock signal.
Claim 8
Dependent Claim
50 words
The apparatus of claim 5, wherein said frequency multiplier means output signal comprises a plurality of clock pulses each having a selectable duty cycle relative to said clock signal, said apparatus further including: duty cycle control means, for controlling the duty cycle of each of said plurality of clock pulses.
Claim 9
Dependent Claim
40 words
The apparatus of claim 6, wherein: said multiplier means output signal comprises first and second clock pulses for each clock signal; and said duty cycle control means maintains a substantially equal duty cycle between said first and second clock pulses.
Claim 10
Dependent Claim
50 words
The apparatus of claim 5, wherein said multiplier means comprises: means for providing at least one delay signal having a selected phase relationship to said clock signal, and having a selected delay from said clock signal; and means for combining said at least one delay signal and said clock signal.
Claim 11
Dependent Claim
47 words
The apparatus of claim 6, wherein said duly cycle control means comprises: means for determining a deviation of the duty cycle of said multiplier output signal from a predetermined duty cycle; and means for adjusting the duty cycle of said clock signal in response to said deviation.
References Cited (Backward Citations)
US3493884A
Cited
US4021740A
Cited
US4185245A
Cited
US4439689A
Cited
US4754166A
Cited
GB2120878A
Cited
EP0103404A2
Cited
EP0302262A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-15 | 1994-10-15 | 1995-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-15 | 1998-10-15 | 1999-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-15 | 2002-10-15 | 2003-04-16 | $7700.00 | Window Closed / Lapsed |