Patent US1968858A successfully refreshed from Google Patents.
EP0103404A2
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Self-calibrated clock and timing signal generator
Assignee: Xerox Corp
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Filing: 1983-08-11
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Granted: —
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Expires: 2003-08-11
Abstract
Abstract A self-calibrated clock and timing signal generator provides reliable and continuous arbitrary digital waveforms of preselectable edge resolution. The generator comprises a multistage means (16) to produce a time-delayed signal of preselectable edge resolution and having a plurality of series-connected delay stages (6Q). The delays per stage are substantially identical so that the selection of any one of the outlets is representative of a predetermined amount of delay provided to an input signal to the multistage means. Calibrating means is integrally included to develop a control signal which is coupled to each of the stages of the multistage means to continuously maintain the predetermined amount of delay per stage. In the embodiment described, the calibrating means takes the form of an automatic frequency control (AFC) loop (12) wherein the frequency of a voltage controlled oscillator (VCO) (18) is regulated to be equal to that of a reference frequency. The VCO comprises a plurality of series-connected delay stages (30). The control voltage is applied to each stage to control the period or frequency of the VCO. The control voltage developed to adjust the VCO frequency is also employed to regulate the delay of the stages (60) comprising the multistage means. The stages of the delay line are identical in construction to the stages of the VCO.
Inventors
- 👤 Alan G. Bell
- 👤 Richard F. Lyon
- 👤 Gaetano Borriello
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 19:42
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315; H03K5/00; H03K5/15; H03L7/085; H03L7/089; H03L7/0891; H03L7/099; H03L7/0995
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
110 words
A self-calibrated clock and timing signal generator (10) to provide arbitrary digital waveforms of preselected edge resolution comprising multistage means (16) to produce a time-delayed signal of preselectable edge resolution from a plurality of outlets between successively coupled delay stages (60) comprising said multistage means, the delays per stage of said multistage means being equal so that the selection of any one of said outlets is representative of a predetermined amount of delay provided to an input signal to said multistage means, and calibration means (12) to develop a control signal and apply said control signal to said multistage means to continuously maintain said predetermined amount of delay per stage.
Claim 2
Dependent Claim
110 words
A self-calibrated clock and timing signal generator (10) to provide arbitrary digital waveforms of preselected edge resolution comprising multistage means (16) to produce a time-delayed signal of preselectable edge resolution from a plurality of outlets between successively coupled delay stages (60) comprising said multistage means, the delays per stage of said multistage means being equal so that the selection of any one of said outlets is representative of a predetermined amount of delay provided to an input signal to said multistage means, and calibration means (12) to develop a control signal and apply said control signal to said multistage means to continuously maintain said predetermined amount of delay per stage.
Claim 3
Dependent Claim
32 words
The self-calibrated clock and timing signal generator of claim 1 wherein said calibrating means includes a plurality of delay stages (30) of identical structure to the delay stages comprising said multistage means.
Claim 4
Dependent Claim
53 words
The self-calibrated clock abd timing signal generator of either claim 1 or 2, wherein said calibrating means is an automatic frequency control loop including a voltage controlled oscillator (18) the control signal developed to drive the delay stages of said oscillator being also employed to drive the delay stages of said delay means.
Claim 5
Dependent Claim
50 words
The self-calibrated clock and timing signal generator of any preceding claim, wherein said calibrting means is an automatic frequency control loop including a voltage controlled oscillator, the control signal developed to drive the delay stages of said oscillator being also employed to drive the delay stages of said multistage means.
Claim 6
Dependent Claim
119 words
The self-calibrated clock and timing signal generator of claim 3 or 4 wherein said automatic frequency control loop comprises means (22) to compare the operating frequency of said voltage controlled oscillator with a reference frequency and develop an output representative of any difference therebetween, and means to produce a control voltage being said control signal and representative of said difference to adjust the voltage controlled oscillator to be the same as that of said reference frequency whereby the adjustment made to the unit delay provided by all of said selay stages is uniform and independent of any differences in the physical and electrical characteristic that may be present in the circuitry comprising said self-calibrated clock and timing signal generator.
Claim 7
Dependent Claim
19 words
The self-calibrated clock and timing signal generator of claim 5 wherein said comparing means includes a frequency divider (20).
Claim 8
Dependent Claim
173 words
A self-calibrating clock and timing signal generator integratable into on-chip circuitry to provide arbitrary digital waveforms of preselected edge resolution comprising frequency generator (12) the frequency of which is calibrated according to a comparison with a reference frequency to develop a control signal, a signal delay means (16) comprising a plurality of delay stages (60) and having a signal input for presentation of an arbitrary digital signal and having a plurality of outputs each representative of a selected time delay provided to said signal presented at said input, the resolution of the delay being substantially equal from stage to stage so that the total delay at any one of said outputs is equal to the number of stages coupled to said output, said control signal coupled to each of the stages of said delay means to control the rate of propagation of said input signal through said delay means whereby the rate of propagation of said input signal through said delay means is continuously calibrated using the reference frequency of said generator means.
Claim 9
Dependent Claim
173 words
A self-calibrating clock and timing signal generator integratable into on-chip circuitry to provide arbitrary digital waveforms of preselected edge resolution comprising frequency generator (12) the frequency of which is calibrated according to a comparison with a reference frequency to develop a control signal, a signal delay means (16) comprising a plurality of delay stages (60) and having a signal input for presentation of an arbitrary digital signal and having a plurality of outputs each representative of a selected time delay provided to said signal presented at said input, the resolution of the delay being substantially equal from stage to stage so that the total delay at any one of said outputs is equal to the number of stages coupled to said output, said control signal coupled to each of the stages of said delay means to control the rate of propagation of said input signal through said delay means whereby the rate of propagation of said input signal through said delay means is continuously calibrated using the reference frequency of said generator means.
Claim 10
Independent Claim
46 words
The method of providing arbitrary digital waveforms of preselected edge resolution comprising the steps of producing a time delay signal of said preselectable edge resolution from a plurality of successively coupled delay stages, calibrating the delay per stage so that the unit delay per stage is
Claim 11
Independent Claim
46 words
The method of providing arbitrary digital waveforms of preselected edge resolution comprising the steps of producing a time delay signal of said preselectable edge resolution from a plurality of successively coupled delay stages, calibrating the delay per stage so that the unit delay per stage is
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