Reset circuit for integrated injection logic

Claim 2

A transistor circuit having an output terminal for providing an output signal for resetting an I 2 L circuit, comprising: a first terminal and a second terminal; a series circuit of first and second resistors coupled between said first terminal and said second terminal; a series circuit of third and fourth resistors coupled between said first and second terminals, the ratio of the resistance value of said first resistor to that of said second resistor being larger than the ratio of the resistance value of said third resistor to that of said fourth resistor; a first transistor having a base, collector, and emitter, and whose collector-emitter path is coupled between the junction of said third and fourth resistors and the second terminal, said emitter of said first transistor being directly connected to the second terminal, said second resistor being directly connected to said emitter, and said first transistor being on-off controlled by a potential appearing at the junction of said first and second resistors; a second transistor having a base, collector, and emitter, and whose collector-emitter path is coupled between the output terminal and the second terminal, said emitter of said second transistor being directly connected to the second terminal, said fourth resistor being directly connected to said emitter, said said second transistor being on-off controlled by a potential appearing at the junction of said third and fourth resistors; and an I 2 L circuit connected to the output terminal and being reset by operation of the transistor circuit.

Claim 3

The transistor circuit of claim 1, wherein said first transistor is a bipolar transistor having a given base-emitter threshold voltage, and said second transistor is a bipolar transistor whose conductivity type is the same as said first transistor and whose base-emitter threshold voltage is substantially the same as the base-emitter threshold voltage of said first transistor.

Claim 4

The transistor circuit of claim 1, wherein one of said first and second transistors is a bipolar type and the other of them is an MOS type.

Claim 5

The transistor circuit of claim 1, wherein said first terminal is coupled to a power source line of the transistor circuit, and said second terminal is coupled to a circuit ground line.

Claim 6

The transistor circuit of claim 1 further comprising a third transistor whose base is coupled to said first terminal, and whose emitter is coupled via said first resistor to the base of said first transistor and via said third resistor to the base of said second transistor.

Claim 7

The transistor circuit of claim 5 wherein a first potential applied to said first resistor is smaller than a second potential applied to said third resistor.

Claim 8

The transistor circuit of claim 1 further comprising a current source connected to said first terminal, and wherein said I 2 L circuit is connected between said current source and said second terminal and has a gate connected to the output terminal.

Claim 9

A transistor circuit having an output terminal for providing an output signal for resetting an I 2 L circuit, comprising: a first terminal and a second terminal; a series circuit of first and second resistors coupled between said first terminal and said second terminal; a series circuit of third and fourth resistors coupled between said first and second terminals, the ratio of the resistance value of said first resistor to that of said second resistor being larger than the ratio of the resistance value of said third resistor to that of said fourth resistor; a first MOS transistor having a gate, drain and source, and whose drain-source path is coupled between the junction of said third and fourth resistors and the second terminal, said source of said first transistor being directly connected to the second terminal, said second resistor being directly connected to said source, and said first transistor being on-off controlled by a potential appearing at the junction of said first and second resistors; a second MOS transistor having a gate, drain and source, and whose conductivity type is the same as said first transistor and drain-source path is coupled between the output terminal and the second terminal, said source of said second transistor being directly connected to the second terminal, said fourth resistor being directly connected to said source, and said second transistor being on-off controlled by a potential appearing at the junction of said third and fourth resistors; both of said MOS transistors being of the enhancement type and having substantially the same gate-source threshold voltage; and an I 2 L circuit connected to the output terminal and being reset by operation of the transistor circuit.

Claim 10

A transistor circuit having an output terminal for providing an output signal for resetting an I 2 L circuit, comprising: a first terminal and a second terminal; a series circuit of first and second resistors coupled between said first terminal and said second terminal; a series circuit of third and fourth resistors coupled between said first and second terminals, the ratio of the resistance value of said first resistor to that of said second resistor being larger than the ratio of the resistance value of said third resistor to that of said fourth resistor; a first MOS transistor having a gate, drain and source, and whose drain-source path is coupled between the junction of said third and fourth resistors and the second terminal, said source of said first transistor being directly connected to the second terminal, said second resistor being directly connected to said source, and said first transistor being on-off controlled by a potential appearing at the junction of said first and second resistors; a second MOS transistor having a gate, drain and source, and whose conductivity type is the same as said first transistor and drain-source path is coupled between the output terminal and the second terminal, said source of said second transistor being directly connected to the second terminal, said fourth resistor being directly connected to said source, and said second transistor being on-off controlled by a potential appearing at the junction of said third and fourth resistors; both of said MOS transistors being of the enhancement type and having substantially the same gate-source threshold voltage; and an I 2 L circuit connected to the output terminal and being reset by operation of the transistor circuit.

Claim 11

A transistor circuit having an output terminal for providing an output signal for resetting an I 2 L circuit, comprising: a first terminal and a second terminal; an input transistor having a base, collector and emitter and whose base is coupled to said first terminal; a series circuit of first and second resistors coupled between said emitter and said second terminal; a series circuit of third and fourth resistors coupled between said emitter and said second terminal, the ratio of the resistance value of said first resistor to that of said second resistor being larger than the ratio of the resistance value of said third resistor to that of said fourth resistor; a series circuit of fifth and sixth resistors coupled between said emitter and said second terminal; a first transistor having a base, collector, and emitter, and whose conduction path is coupled between the junction of said third and fourth resistors and the second terminal, said emitter of said first transistor being directly connected to the second terminal, said second resistor being directly connected to said emitter, and said first transistor being on-off controlled by a potential appearing at the junction of said first and second resistors: a second transistor having a base, collector, and emitter, and whose conduction path is coupled between the junction of said fifth and sixth resistors and the second terminal, said emitter of said second transistor being directly connected to the second terminal, said fourth resistor being directly connected to said emitter, and said second transistor being on-off controlled by a potential appearing at the junction of said third and fourth resistors; a third transistor whose conduction path is coupled between the output terminal and said second terminal, said third transistor being on-off controlled by a potential appearing at the junction of said fifth and sixth resistors; and an I 2 L circuit connected to the output terminal and being reset by operation of the transistor circuit.

Claim 12

A transistor circuit having an output terminal for providing an output signal for resetting an I 2 L circuit, comprising: a first terminal and a second terminal; an input transistor having a base, collector and emitter and whose base is coupled to said first terminal; a series circuit of first and second resistors coupled between said emitter and said second terminal; a series circuit of third and fourth resistors coupled between said emitter and said second terminal, the ratio of the resistance value of said first resistor to that of said second resistor being larger than the ratio of the resistance value of said third resistor to that of said fourth resistor; a series circuit of fifth and sixth resistors coupled between said emitter and said second terminal; a first transistor having a base, collector, and emitter, and whose conduction path is coupled between the junction of said third and fourth resistors and the second terminal, said emitter of said first transistor being directly connected to the second terminal, said second resistor being directly connected to said emitter, and said first transistor being on-off controlled by a potential appearing at the junction of said first and second resistors: a second transistor having a base, collector, and emitter, and whose conduction path is coupled between the junction of said fifth and sixth resistors and the second terminal, said emitter of said second transistor being directly connected to the second terminal, said fourth resistor being directly connected to said emitter, and said second transistor being on-off controlled by a potential appearing at the junction of said third and fourth resistors; a third transistor whose conduction path is coupled between the output terminal and said second terminal, said third transistor being on-off controlled by a potential appearing at the junction of said fifth and sixth resistors; and an I 2 L circuit connected to the output terminal and being reset by operation of the transistor circuit.

Claim 13

The transistor circuit of claim 6, further comprising means coupled to said third transistor for shifting said second potential so that the potential difference between said first and second potentials increases.