US3725675A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power sequencing control circuit
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1971-03-29
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Granted: 1973-04-03
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Expires: 1991-03-29
Abstract
Abstract Current applied to a load by means of a first voltage is disabled by control means in response to a change of a second voltage by a predetermined value. The control means is powered by the first voltage and includes two stages, a first for detecting a change of the second voltage and the second responsive to such change and powered by the first voltage for generating a signal for disabling the current applied to the load.
Inventors
- 👤 R Olsen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:46
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/577
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
159 words
A control circuit for a memory system which system includes addressing means and timing means powered by a second voltage source, current switch means powered by a first voltage source, said addressing means and said timing means coupled to enable said current switch means, and a memory selection line coupled to receive current by means of said current switch means and by means of said first voltage source, wherein said circuit is utilized for inhibiting said current in said selection line when said second voltage changes below a predetermined value, said circuit Comprising: A. a first circuit stage which produces a first signal when said second voltage source changes below said predetermined value; B. a second circuit stage powered by said first voltage source and responsive to said first signal for producing a second signal; and C. means coupling said second circuit stage to said current switch means so that the presence of said second signal inhibits said current.
Claim 2
Dependent Claim
159 words
A control circuit for a memory system which system includes addressing means and timing means powered by a second voltage source, current switch means powered by a first voltage source, said addressing means and said timing means coupled to enable said current switch means, and a memory selection line coupled to receive current by means of said current switch means and by means of said first voltage source, wherein said circuit is utilized for inhibiting said current in said selection line when said second voltage changes below a predetermined value, said circuit Comprising: A. a first circuit stage which produces a first signal when said second voltage source changes below said predetermined value; B. a second circuit stage powered by said first voltage source and responsive to said first signal for producing a second signal; and C. means coupling said second circuit stage to said current switch means so that the presence of said second signal inhibits said current.
Claim 3
Dependent Claim
103 words
A circuit as defined in claim 1 wherein: A. said first circuit stage comprises a first transistor means which is turned on when said second voltage source is at its normal value and which is turned off producing said first signal when said second voltage source changes below a predetermined value, and wherein B. said second circuit stage comprises a second transistor means which is turned off when said first transistor means is turned on and which is turned on by said first voltage source in response to said first signal, said first signal produced when said second transistor means is turned on.
Claim 4
Dependent Claim
22 words
a second circuit stage powered by said first voltage source and responsive to said first signal for producing a second signal; and
Claim 5
Dependent Claim
22 words
a second circuit stage powered by said first voltage source and responsive to said first signal for producing a second signal; and
Claim 6
Dependent Claim
18 words
timing means, wherein said second voltage source provides power to said addressing means and said timing means, and
Claim 7
Dependent Claim
18 words
timing means, wherein said second voltage source provides power to said addressing means and said timing means, and
Claim 8
Dependent Claim
23 words
means for coupling said second circuit stage to said current switch means so that the presence of said second signal inhibits said current.
Claim 9
Dependent Claim
23 words
means for coupling said second circuit stage to said current switch means so that the presence of said second signal inhibits said current.
Claim 10
Dependent Claim
45 words
means for coupling said addressing means and said timing means to enable said current switch means; F. a control circuit for inhibiting said current in said selection line when the value of said second voltage source changes by a predetermined amount, said control circuit comprising:
Claim 11
Dependent Claim
45 words
means for coupling said addressing means and said timing means to enable said current switch means; F. a control circuit for inhibiting said current in said selection line when the value of said second voltage source changes by a predetermined amount, said control circuit comprising:
Claim 12
Dependent Claim
44 words
A memory system comprising: A. current switch means; B. a first voltage source; C. a memory selection line coupled to receive current by means of said current switch means and said first voltage source; D. a second voltage source; E. first circuit means comprising:
Claim 13
Dependent Claim
44 words
A memory system comprising: A. current switch means; B. a first voltage source; C. a memory selection line coupled to receive current by means of said current switch means and said first voltage source; D. a second voltage source; E. first circuit means comprising:
Claim 14
Dependent Claim
85 words
A circuit as defined in claim 3 wherein: A. said first circuit stage includes a first transistor having a base, a collector and an emitter electrode; B. said second circuit stage includes a second transistor having a base, a collector and an emitter electrode; C. wherein said second voltage source is coupled to said base electrode of said fist transistor; and D. wherein said first voltage source is coupled to said collector electrode of said first transistor and said base electrode of said second transistor.
Claim 15
Dependent Claim
22 words
A circuit as defined in claim 4 wherein said collector electrode of said second transistor is coupled to said current switch means.
Claim 16
Dependent Claim
83 words
A circuit as defined in claim 5 further comprising: A. first resistive means coupled to receive said second voltage source at one end and coupled at the other end to said first transistor base electrodes; B. second resistive means coupled to receive said first voltage source at one end and coupled at the other end to said first transistor collector electrode and said second transistor base electrode; and wherein C. said first and second transistor emitter electrodes are coupled to a third voltage.
Claim 17
Dependent Claim
44 words
A circuit as defined in claim 6 further comprising: A. Zener diode means coupled in the coupling between said first resistive means and said first transistor base electrode; and B. fourth resistive means coupled between said first transistor base electrode and said third voltage.
Claim 18
Dependent Claim
30 words
A circuit as defined in claim 6 further comprising a third resistive means coupled at one end to said output terminal and at the other end to a fourth voltage.
Claim 19
Dependent Claim
15 words
A circuit as defined in claim 8 wherein said second and fourth voltages are equivalent.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-02 | 1976-10-02 | 1977-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-02 | 1980-10-02 | 1981-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-02 | 1984-10-02 | 1985-04-03 | $7700.00 | Window Closed / Lapsed |