US3560767A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay circuit arrangement
Assignee: Grundig EMV Elektromechanische Versuchsanstalt Max Grundig GmbH
•
Filing: 1969-03-19
•
Granted: 1971-02-02
•
Expires: 1989-03-19
Abstract
Abstract An arrangement for delaying the application of a voltage supply for a predetermined time interval. An auxiliary voltage supply of identical polarity and with one terminal at a level exceeding the level of the terminal which is common to the supplies, is applied across a voltage divider. A first transistor is connected to a tap or junction of the voltage divider through its base. The emitter-collector path of this first transistor is connected across the voltage divider and the auxiliary power supply. A second transistor of opposite conductivity type relative to the first transitor is connected with its emitter to the terminal common to the two power supplies, as well as the emitter of the first transistor. The base of the second transistor is connected to a second voltage divider connected to the collector of the first transistor. Through a capacitor connected in parallel with a portion of the first voltage divider connected across the auxiliary power supply, an RC network is realized which delays the application of the voltage appearing at the collector of the second transistor, for a selected predetermined time interval.
Inventors
- 👤 Karl Traub
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:32
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/28
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
194 words
A delay circuit arrangement comprising, in combination, a first source of voltage to be transmitted after a predetermined time interval, said first source of voltage having a reference terminal and a first potential terminal; a second source of voltage having a second potential terminal, the magnitude of the potential of said second potential terminal exceeding the magnitude of the potential of said first potential terminal, the polarity of said first terminal being identical to the polarity of said second terminal; voltage-dividing means connected between said first potential terminal and said second potential terminal; a first transistor with emitter-collector path connected in parallel with said voltage dividing means; capacitor means connected in parallel with a portion of said voltage-dividing means; a second transistor with base connected to the collector of said first transistor, said second transistor being opposite in conductivity type to said first transistor; means for connecting the collector of said first transistor to said voltage-dividing means and means for connecting the emitters of said transistors to said voltage-dividing means, whereby a desired potential appears at the collector of said second transistor a predetermined time interval after the application of said source of voltage.
Claim 2
Dependent Claim
194 words
A delay circuit arrangement comprising, in combination, a first source of voltage to be transmitted after a predetermined time interval, said first source of voltage having a reference terminal and a first potential terminal; a second source of voltage having a second potential terminal, the magnitude of the potential of said second potential terminal exceeding the magnitude of the potential of said first potential terminal, the polarity of said first terminal being identical to the polarity of said second terminal; voltage-dividing means connected between said first potential terminal and said second potential terminal; a first transistor with emitter-collector path connected in parallel with said voltage dividing means; capacitor means connected in parallel with a portion of said voltage-dividing means; a second transistor with base connected to the collector of said first transistor, said second transistor being opposite in conductivity type to said first transistor; means for connecting the collector of said first transistor to said voltage-dividing means and means for connecting the emitters of said transistors to said voltage-dividing means, whereby a desired potential appears at the collector of said second transistor a predetermined time interval after the application of said source of voltage.
Claim 3
Dependent Claim
17 words
The delay circuit arrangement as defined in claim 1 wherein said reference terminal is at ground potential.
Claim 4
Dependent Claim
18 words
The delay circuit arrangement as defined in claim 1 wherein said first potential terminal is at positive potential.
Claim 5
Dependent Claim
18 words
The delay circuit arrangement as defined in claim 1 wherein said first potential terminal is at negative potential.
Claim 6
Dependent Claim
19 words
The delay circuit arrangement as defined in claim 1 wherein said voltage-dividing means comprises two resistors connected in series.
Claim 7
Dependent Claim
26 words
The delay circuit arrangement as defined in claim 5 wherein said capacitor means is connected in parallel with one of the resistors of said voltage-dividing means.
Claim 8
Dependent Claim
26 words
The delay circuit arrangement as defined in claim 1 including means for connecting the base of said first transistor to the junction of said voltage-dividing means.
Claim 9
Dependent Claim
35 words
The delay circuit arrangement as defined in claim 1 wherein said means for connecting said emitters of said transistors to said voltage-dividing means comprises a resistor connecteD between said first potential terminal and said emitters.
Claim 10
Dependent Claim
38 words
The delay circuit arrangement as defined in claim 1 including second voltage-dividing means connected between the collector of said first transistor and said reference terminal, the base of said second transistor being connected to said second voltage-dividing means.
Claim 11
Dependent Claim
40 words
The delay circuit arrangement as defined in claim 9 wherein said second voltage-dividing means comprises two resistors connected in series, the junction of said two resistors of said second voltage-dividing means being connected to the base of said second transistor.
Claim 12
Dependent Claim
27 words
The delay circuit arrangement as defined in claim 7 wherein said means for connecting the base of said first transistor to said voltage-dividing means comprises a resistor.
Claim 13
Dependent Claim
27 words
The delay circuit arrangement as defined in claim 1 wherein said means for connecting the collector of said first transistor to said voltage-dividing means comprises a resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-01 | 1974-08-03 | 1975-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-01 | 1978-08-03 | 1979-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-01 | 1982-08-03 | 1983-02-02 | $7700.00 | Window Closed / Lapsed |