High speed partioned reduced instruction set computer

Claim 2

A logic circuit comprising: a plurality of integrated circuits, each containing circuitry carrying out operations syn­chronized to a clock signal; means for generating a master clock signal; a plurality of delay circuits, each for producing a separate output clock signal in adjust­ably delayed response to said master clock signal; and means for conveying the output clock sig­nal produced by each delay circuit to a separate one of said integrated circuits for synchronizing operations of circuitry contained therein.

Claim 3

The logic circuit in accordance with claim 1 wherein at least one of said plurality of inte­grated circuits contains circuitry comprising bi­polar transistors.

Claim 4

The logic circuit in accordance with claim 1 wherein at least one of said plurality of inte­grated circuits contains current tree logic cir­cuitry.

Claim 5

A logic circuit comprising: a plurality of integrated circuits, each for producing at least one output data signal and re­ceiving at least one input data signal in synchronous relation to a clock signal; means for generating a master clock signal; a plurality of delay circuits, each for producing in response to said master clock signal a separate output clock signal in adjustably delayed response to said master clock signal; and means for conveying ones of said input and output data signals between pairs of said inte­grated circuits and for conveying the output clock signal produced by each delay circuit to a separate one of said integrated circuits.

Claim 6

A logic circuit comprising: a plurality of integrated circuits, each for producing at least one output data signal and re­ceiving at least one input data signal in synchronous relation to a clock signal; means for generating a master clock signal; a plurality of delay circuits, each for producing in response to said master clock signal a separate output clock signal in adjustably delayed response to said master clock signal; and means for conveying ones of said input and output data signals between pairs of said inte­grated circuits and for conveying the output clock signal produced by each delay circuit to a separate one of said integrated circuits.

Claim 7

The logic circuit in accordance with claim 4 wherein said means for conveying signals comprises: a plurality of dielectric films; and a plurality of conductor planes, said dielectric films juxtaposed therebetween, each said conductor plane comprising at least one con­ductor, conductors pairs of separate planes forming constant impedance transmission lines for conveying said input and output data signals and the output clock signals.

Claim 8

The logic circuit in accordance with claim 5 wherein said dielectric films comprise polyimide film.

Claim 9

A computer processor comprising: a plurality of dielectric films; a plurality of conductor planes, each comprising at least one conductor, ones of said dielectric films being inserted between said conductor planes such that conductors of separate ones of said conductor planes form transmission lines for conveying signals, said transmission lines forming a first bus, a second bus, and a third bus; means for selectively transmitting data signals conveyed on said third busses to said first bus; a dual port addressable register file for receiving and storing data signals and for reading out stored data signals, said register file having a first port for receiving data signals conveyed on said first bus and for reading out data signals onto said second bus, and having a second port for receiving data signals conveyed on said third bus and for reading out data signals onto said third bus; arithmetic logic means for performing operations on data signals appearing on said second and third busses to produce output data signals; and means for selectively placing said output data signals on said third bus.

Claim 10

A computer processor comprising: a plurality of dielectric films; a plurality of conductor planes, each comprising at least one conductor, ones of said dielectric films being inserted between said conductor planes such that conductors of separate ones of said conductor planes form transmission lines for conveying signals, said transmission lines forming a first bus, a second bus, and a third bus; means for selectively transmitting data signals conveyed on said third busses to said first bus; a dual port addressable register file for receiving and storing data signals and for reading out stored data signals, said register file having a first port for receiving data signals conveyed on said first bus and for reading out data signals onto said second bus, and having a second port for receiving data signals conveyed on said third bus and for reading out data signals onto said third bus; arithmetic logic means for performing operations on data signals appearing on said second and third busses to produce output data signals; and means for selectively placing said output data signals on said third bus.

Claim 11

The computer processor in accordance with claim 7 further comprising a plurality of delay cir­cuits, each for producing a separate output clock signal in adjustably delayed response to said mas­ter clock signal, the output clock signals produced by said delay circuits being conveyed by said transmission lines to separate ones of said plu­rality integrated circuits for synchronizing opera­tions thereof.

Claim 12

The computer processor in accordance with claim 7 wherein said dielectric films comprise polyimide film.

Claim 13

A computer processor comprising: a first bus for conveying first data sig­nals; a second bus for conveying second data signals; a third bus for conveying third data sig­nals; dual port addressable register means for storing data signals conveyed on said first and third busses, having a first port for receiving said first data signals conveyed on said first bus and for reading out stored data signals onto said second bus, and having a second port for receiving said third data signal conveyed on said third bus and for reading out stored data signals onto said third bus; means for selectively conveying third data signals to said first bus; arithmetic logic unit means for producing output data signals comprising programmably deter­mined combinations of said second and third data signals; and means for selectively conveying said output data signals to said third bus.

Claim 14

A computer processor comprising: a first bus for conveying first data sig­nals; a second bus for conveying second data signals; a third bus for conveying third data sig­nals; dual port addressable register means for storing data signals conveyed on said first and third busses, having a first port for receiving said first data signals conveyed on said first bus and for reading out stored data signals onto said second bus, and having a second port for receiving said third data signal conveyed on said third bus and for reading out stored data signals onto said third bus; means for selectively conveying third data signals to said first bus; arithmetic logic unit means for producing output data signals comprising programmably deter­mined combinations of said second and third data signals; and means for selectively conveying said output data signals to said third bus.

Claim 15

A computer processor comprising: a plurality of dielectric films; a plurality of conductor planes, each comprising at least one conductor, ones of said dielectric films being inserted between said conductor planes such that conductors of separate ones of said conductor planes form transmission lines for conveying signals, said transmission lines forming a first bus, a second bus, and a third bus; at least one first integrated circuit comprising dual port addressable register means for storing data signals conveyed on said first and third busses, having a first port for receiving said first data signals conveyed on said first bus and for reading out stored data signals onto said second bus, and having a second port for receiving said third data signal conveyed on said third bus and for reading out stored data signals onto said third bus; and at least one second integrated circuit comprising arithmetic logic unit means for pro­ducing output data signals comprising programmably determined combinations of said second and third data signals, and means for selectively conveying said output data signals to said third bus.

Claim 16

A computer processor comprising: a plurality of dielectric films; a plurality of conductor planes, each comprising at least one conductor, ones of said dielectric films being inserted between said conductor planes such that conductors of separate ones of said conductor planes form transmission lines for conveying signals, said transmission lines forming a first bus, a second bus, and a third bus; at least one first integrated circuit comprising dual port addressable register means for storing data signals conveyed on said first and third busses, having a first port for receiving said first data signals conveyed on said first bus and for reading out stored data signals onto said second bus, and having a second port for receiving said third data signal conveyed on said third bus and for reading out stored data signals onto said third bus; and at least one second integrated circuit comprising arithmetic logic unit means for pro­ducing output data signals comprising programmably determined combinations of said second and third data signals, and means for selectively conveying said output data signals to said third bus.

Claim 17

A computer processor implemented as a plurality of integrated circuits, ones of said integrated circuits operating in timed relation to a pulsed clock signal transmitted thereto, said processor comprising: arithmetic logic unit means for producing an output data signal representing a combination of a plurality of input data signals; multiple port register file means for supplying said input data signals to said arithme­tic logic unit means and for storing data conveyed by said output data signals, said multiple port register file means and said arithmetic logic unit means being implemented by separate ones of said integrated circuits; signal transmission means comprising metallic conductors separated by dielectric films forming transmission lines for conveying said input data signals and said output data signals between said register file means and said arithmetic logic means, and for conveying said clock signal to said ones of said integrated circuits; and means for adjustably delaying conveyance of each pulse of said clock signal to each of said ones of said integrated circuits so that each said pulse arrives simultaneously at each of said ones of said integrated circuits.

Claim 18

A computer processor implemented as a plurality of integrated circuits, ones of said integrated circuits operating in timed relation to a pulsed clock signal transmitted thereto, said processor comprising: arithmetic logic unit means for producing an output data signal representing a combination of a plurality of input data signals; multiple port register file means for supplying said input data signals to said arithme­tic logic unit means and for storing data conveyed by said output data signals, said multiple port register file means and said arithmetic logic unit means being implemented by separate ones of said integrated circuits; signal transmission means comprising metallic conductors separated by dielectric films forming transmission lines for conveying said input data signals and said output data signals between said register file means and said arithmetic logic means, and for conveying said clock signal to said ones of said integrated circuits; and means for adjustably delaying conveyance of each pulse of said clock signal to each of said ones of said integrated circuits so that each said pulse arrives simultaneously at each of said ones of said integrated circuits.

Claim 19

The computer processor in accordance with claim 12 wherein said arithmetic logic unit means comprises circuitry containing bipolar transistors.

Claim 20

The computer processor in accordance with claim 12 wherein said transmission lines have sub­stantially constant impedance.