Single-edge clock adjustment circuits for PLL-compatible, dynamic duty-cycle correction circuits

Claim 2

A duty cycle correction circuit comprising: a delay-control circuit configured to receive a first clock signal and generate a delay-control voltage, wherein the first clock signal consists of a train of clock pulses, each of which clock pulses has a rising clock edge and a falling clock edge, the delay-control circuit including: a first voltage divider configured to receive the first clock signal and generate a first output voltage representing a dc average of the first clock signal; a second voltage divider configured to generate a second output voltage; a differential amplifier having first and second input terminals and an output terminal, wherein the first input terminal is coupled to the first voltage divider to receive the first output voltage, wherein the second input terminal is coupled to the second voltage divider to receive the second output voltage, and wherein the output terminal outputs a third output voltage; and a stability circuit coupled to the output terminal to receive the third output voltage and generate the delay-control voltage by stabilizing the third output voltage; and a clock-inverter circuit configured to receive a second clock signal and the delay-control voltage and to generate a third clock signal, wherein the clock-inverter circuit is biased with first and second bias voltages, the clock-inverter circuit including: a first field effect transistor (FET) having a source, a gate, and a drain, wherein the gate of the first FET is coupled to the delay-control voltage, and wherein the source of the first FET is coupled to the first bias voltage; a second FET having a source, a gate, and a drain, wherein the source of the second FET is coupled to the first bias voltage, wherein the gate of the second FET receives the second clock signal, and wherein the drain of the second FET outputs the third clock signal; a third FET having a source, a gate, and a drain, wherein the source of the third FET is coupled to the drain of the first FET, wherein the gate of the third FET is coupled to the gate of the second FET, and wherein the drain of the third FET is coupled to the drain of the second FET; and a fourth FET having a source, a gate, and a drain, wherein the source of the fourth FET is coupled to the second bias voltage, wherein the gate of the fourth FET is coupled to the gates of the second and third FETs, and wherein the drain of the fourth FET is coupled to the drains of the second and third FETs.

Claim 3

The duty cycle correction circuit of claim 1 , wherein the first clock signal is a feedback signal of the third clock signal.

Claim 4

The duty cycle correction circuit of claim 1 , wherein the first voltage divider comprises: a first transistor inverter configured to receive the first clock signal and generate an inverted version of the first clock signal; first and second capacitors coupled in series between a supply voltage and ground, wherein the first and second capacitors have a substantially identical capacitance; and a first resistor coupled between an output of the first transistor inverter and a connection point between the first and second capacitors, wherein the first output voltage is applied between the connection point and ground.

Claim 5

The duty cycle correction circuit of claim 3 , wherein the first transistor inverter comprises fifth and sixth FETs, the fifth and sixth FETs each having a source, a gate, and a drain, wherein the source of the fifth FET is coupled to the supply voltage, wherein the drain of the fifth FET is coupled to the drain of the sixth FET to form the output of the first transistor inverter, wherein the source of the sixth FET is coupled to ground, and wherein the gates of the fifth and sixth FETs are coupled together to receive the first clock signal.

Claim 6

The duty cycle correction circuit of claim 4 , wherein the fifth and sixth FETs are respectively p-channel and n-channel FETs.

Claim 7

The duty cycle correction circuit of claim 4 wherein the fifth and sixth FETs have approximately equal device strengths.

Claim 8

The duty cycle correction circuit of claim 4 wherein the resistance of the first resistor is much larger than the resistances of the fifth and sixth FETs.

Claim 9

The duty cycle correction circuit of claim 3 wherein a time constant formed by the first resistor and one of the first and second capacitors is much larger than the clock period of the first clock signal.

Claim 10

The duty cycle correction circuit of claim 1 , wherein the second voltage divider comprises: a seventh FET having a source, a gate, and a drain, wherein the seventh FET is a p-channel FET, wherein the source of the seventh FET is coupled to a supply voltage, and wherein the gate of the seventh FET receives a first control bit; an eighth FET having a source, a gate, and a drain, wherein the eighth FET is an n-channel FET, wherein the source of the eighth FET is coupled to ground, and wherein the gate of the eighth FET receives a second control bit; second and third resistors coupled in series between the drain of the seventh FET and the drain of the eighth FET, the second resistor being coupled to the third resistor at a node to which the second output voltage is applied; fourth and fifth resistors coupled in series between the supply voltage and ground, the fourth resistor being coupled to the fifth resistor at the node to which the second output voltage is applied; and third and fourth capacitors coupled in series between the supply voltage and ground, the third capacitor being coupled to the fourth capacitor at the node to which the second output voltage is applied.

Claim 11

The duty cycle correction circuit of claim 9 , wherein the second and third resistors have a substantially identical resistance, wherein the fourth and fifth resistors have a substantially identical resistance, wherein the resistance of the second resistor is much greater than the resistance of the fourth resistor, and wherein the seventh and eighth FETs are much stronger than the second and third resistors.

Claim 12

The duty cycle correction circuit of claim 9 , wherein the first and second control bits control the duty cycle of the first and third clock signals in a steady state.

Claim 13

The duty cycle correction circuit of claim 9 , wherein the first and second control bits control the duty cycle of the first and third clock signals in a steady state, wherein the duty cycle is fifty percent in a steady state when the first and second control bits have different values, wherein the duty cycle is slightly over fifty percent in a steady state when the first and second control bits have a logical 1 , and wherein the duty cycle is slightly below fifty percent in a steady state when the first and second control bits have a logical 0 .

Claim 14

The duty cycle correction circuit of claim 9 , further comprising: a ninth FET having a source, a gate, and a drain, wherein the ninth FET is a p-channel FET, wherein the source of the seventh FET is coupled to the supply voltage, and wherein the gate of the ninth FET receives a third control bit; a tenth FET having a source, a gate, and a drain, wherein the tenth FET is an n-channel FET, wherein the source of the tenth FET is coupled to ground, and wherein the gate of the tenth FET receives a fourth control bit; and sixth and seventh resistors coupled in series between the drain of the ninth FET and the drain of the tenth FET, the sixth resistor being coupled to the seventh resistor at the node to which the second output voltage is applied.

Claim 15

The duty cycle correction circuit of claim 1 , wherein the first and second input terminals are respectively an inverting input terminal and a non-inverting input terminal of the differential amplifier, and wherein the first clock signal logically equals the third clock signal in a steady state.

Claim 16

The duty cycle correction circuit of claim 1 , wherein the first and second input terminals are respectively a non-inverting input terminal and an inverting input terminal of the differential amplifier, and wherein the first clock signal is an inverted version of the third clock signal in a steady state.

Claim 17

The duty cycle correction circuit of claim 1 , wherein the stability circuit comprises: an eighth resistor coupled between the output terminal of the differential amplifier and a node to which the delay-control voltage is applied; and fifth and sixth capacitors coupled in series between a supply voltage and ground, wherein the fifth and sixth capacitors are coupled to the eighth resistor at the node to which the delay-control voltage is applied.

Claim 18

The duty cycle correction circuit of claim 1 , wherein the first, second, and third FETs are n-channel FETs, wherein the fourth FET is a p-channel FET, wherein the first and second bias voltages are respectively ground and a supply voltage, and wherein the duty cycle correction circuit adjusts the falling clock edge of each clock pulse of the third clock signal, thereby adjusting the duty cycles of the first and third clock signals.

Claim 19

The duty cycle correction circuit of claim 1 , wherein the first, second, and third FETs are p-channel FETs, wherein the fourth FET is a n-channel FET, wherein the first and second bias voltages are respectively a supply voltage and ground, and wherein the duty cycle correction circuit adjusts the rising clock edge of each clock pulse of the third clock signal, thereby adjusting the duty cycles of the first and third clock signals.

Claim 20

A duty cycle correction circuit comprising: a delay-control circuit configured to receive a first clock signal and generate a delay-control voltage, wherein the first clock signal consists of a train of clock pulses, each of which clock pulses has a rising clock edge and a falling clock edge, the delay-control circuit including: a first voltage divider configured to receive the first clock signal and generate a first output voltage representing a dc average of the first clock signal; a second voltage divider configured to generate a second output voltage; a differential amplifier having first and second input terminals and an output terminal, wherein the first input terminal is coupled to the first voltage divider to receive the first output voltage, wherein the second input terminal is coupled to the second voltage divider to receive the second output voltage, and wherein the output terminal outputs a third output voltage; and a stability circuit coupled to the output terminal to receive the third output voltage and generate the delay-control voltage by stabilizing the third output voltage; and a clock-inverter circuit configured to receive a second clock signal and the delay-control voltage and to generate a third clock signal, wherein the clock-inverter circuit is biased with first and second bias voltages, the clock-inverter circuit including: a first field effect transistor (FET) having a source, a gate, and a drain, wherein the gate of the first FET is coupled to the delay-control voltage, and wherein the source of the first FET is coupled to the first bias voltage; a second FET having a source, a gate, and a drain, wherein the source of the second FET is coupled to the first bias voltage; a third FET having a source, a gate, and a drain, wherein the source of the third FET is coupled to the drain of the first FET, wherein the gate of the third FET is coupled to the gate of the second FET, and wherein the drain of the third FET is coupled to the drain of the second FET; a fourth FET having a source, a gate, and a drain, wherein the source of the fourth FET is coupled to the second bias voltage, wherein the gate of the fourth FET is coupled to the gates of the second and third FETs, and wherein the drain of the fourth FET is coupled to the drains of the second and third FETs; a first transistor inverter having fifth and sixth FETs, the fifth and sixth FETs each having a source, a gate, and a drain, wherein the source of the fifth FET is coupled to the second bias voltage, wherein the source of the sixth FET is coupled to the first bias voltage, wherein the drain of the fifth FET is coupled to the drain of the sixth FET, wherein the gates of the fifth and sixth FETs are coupled together to receive the second clock signal, and wherein the drain of the fifth FET is coupled to the gates of the second, third, and fourth FETs; and a second transistor inverter having seventh and eighth FETs, the seventh and eighth FETs each having a source, a gate, and a drain, wherein the source of the seventh FET is coupled to the second bias voltage, wherein the source of the eighth FET is coupled to the first bias voltage, wherein the drain of the seventh FET is coupled to the drain of the eighth FET, wherein the gates of the seventh and eighth FETs are coupled together to the drain of the fourth FET, and wherein the drain of the seventh FET is configured to output the third clock signal.

Claim 21

A duty cycle correction circuit comprising: a delay-control circuit configured to receive a first clock signal and generate a delay-control voltage, wherein the first clock signal consists of a train of clock pulses, each of which clock pulses has a rising clock edge and a falling clock edge, the delay-control circuit including: a first voltage divider configured to receive the first clock signal and generate a first output voltage representing a dc average of the first clock signal; a second voltage divider configured to generate a second output voltage; a differential amplifier having first and second input terminals and an output terminal, wherein the first input terminal is coupled to the first voltage divider to receive the first output voltage, wherein the second input terminal is coupled to the second voltage divider to receive the second output voltage, and wherein the output terminal outputs a third output voltage; and a stability circuit coupled to the output terminal to receive the third output voltage and generate the delay-control voltage by stabilizing the third output voltage; and a clock-inverter circuit configured to receive a second clock signal and the delay-control voltage and to generate a third clock signal, wherein the clock-inverter circuit is biased with first and second bias voltages, the clock-inverter circuit including: a first field effect transistor (FET) having a source, a gate, and a drain, wherein the gate of the first FET is coupled to the delay-control voltage, and wherein the source of the first FET is coupled to the first bias voltage; a second FET having a source, a gate, and a drain, wherein the source of the second FET is coupled to the first bias voltage; a third FET having a source, a gate, and a drain, wherein the source of the third FET is coupled to the drain of the first FET, wherein the gate of the third FET is coupled to the gate of the second FET, and wherein the drain of the third FET is coupled to the drain of the second FET; a fourth FET having a source, a gate, and a drain, wherein the source of the fourth FET is coupled to the second bias voltage, wherein the gate of the fourth FET is coupled to the gates of the second and third FETs, and wherein the drain of the fourth FET is coupled to the drains of the second and third FETs; a first transistor inverter having fifth and sixth FETs, the fifth and sixth FETs each having a source, a gate, and a drain, wherein the source of the fifth FET is coupled to the second bias voltage, wherein the source of the sixth FET is coupled to the first bias voltage, wherein the drain of the fifth FET is coupled to the drain of the sixth FET, wherein the gates of the fifth and sixth FETs are coupled together to receive the second clock signal, and wherein the drain of the fifth FET is coupled to the gates of the second, third, and fourth FETs; and a second transistor inverter having seventh and eighth FETs, the seventh and eighth FETs each having a source, a gate, and a drain, wherein the source of the seventh FET is coupled to the second bias voltage, wherein the source of the eighth FET is coupled to the first bias voltage, wherein the drain of the seventh FET is coupled to the drain of the eighth FET, wherein the gates of the seventh and eighth FETs are coupled together to the drain of the fourth FET, and wherein the drain of the seventh FET is configured to output the third clock signal.